JP2005529482A - 接続層を有する集積回路装置および関連する製造方法 - Google Patents
接続層を有する集積回路装置および関連する製造方法 Download PDFInfo
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- JP2005529482A JP2005529482A JP2004502353A JP2004502353A JP2005529482A JP 2005529482 A JP2005529482 A JP 2005529482A JP 2004502353 A JP2004502353 A JP 2004502353A JP 2004502353 A JP2004502353 A JP 2004502353A JP 2005529482 A JP2005529482 A JP 2005529482A
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Abstract
Description
− 高線形LINキャパシタンス(0.5fF/μm2超または0.7fF/μm2超)、
− 強力結合ブロックコンデンサ、
− 特にRFコイルにおける、高Q値のコイル、
− 強力結合作動電圧給電、
− 外部接続用端子板(配線ボンディングパッド)またはその他のフリップチップ端子板(パッド)、
− レーザヒューズ接続(ヒューズ)
− 最終Cu面および/またはAl面における信号ライン。
他の開発例において、他の処理条件、好ましくはHDP法(高密度プラズマ)やPECVD法(プラズマ促進化学蒸着)を用いて作製された少なくとも2つの層を含む。この方策により、密度が高くなることからエレクトロマイグレーションを防ぐ上で最も達成可能な特性をもつ部分層をまず作製することができる。その後、特に高誘電率の部分層を作製することが可能である。
本発明による方法の他の開発例において、まず1つの接続層が施工される。その後、上部接続層の接続部のカットアウトが施工される。その後に初めて中間層が施工される。この開発例において、上部接続層は例えば銅を含む。
銅でできた下部金属層106,108,102の作製:
− 下部金属層106,108,102は、例えばダマシン技術を用いて低誘電率kの材料中における銅の蒸着または銅合金の蒸着により作製される。さらに、機械的安定性のため、多数の接触穴122〜126がボンディング接続110の下部に配置される。
− 二酸化珪素152またはその他の材料、例えばFSG(蛍石珪酸ガラス)が、リソグラフィ処理を使って施工・パターン化される。ライナ/バリア層150および銅148が引き続いて蒸着される。
− ライナ/バリア層150と銅148はその後、化学的機械的研磨法(CMP)によりほぼ二酸化珪素152の位置まで除去される。引き続いてこの表面は、例えばブラシアシスト洗浄(ブラシ洗浄)により洗浄される。
中間層160の作製に対する変形例:
a)約100nmの窒化珪素を、最上部金属層104に対する誘電拡散バリアとして、さらに金属間誘電体として、たとえばCDV法(化学的蒸着法)またはPECVD法(プラズマ促進CDV)により蒸着する。
− 金属間層160に対してフォトレジストを施工し、接触穴162,164,166に対する構造に応じて露出・現像させる。
−接触穴162,164,166を金属間層160内にエッチングする。
− フォトレジストの残りの部分は除去される。
− 接触穴162,164,166の底部に蒸着した可能性のある酸化銅を除去するため、例えば、湿式洗浄段階で接触穴162,164,166を洗浄する。
− バリア層172が蒸着され、例えばH2に基づくスパッタリング前洗浄または反応性前洗浄を行う、金属拡散バリアに適した材料としては、Ta,TaN,Ti,TiN,W,WN等がある。適した蒸着法としては、PVD法(物理蒸着法)またはCDV法がある。
− アルミニウム170またはアルミニウム合金はPVD法またはCDV法で蒸着される。
− 反射防止層192は、例えば窒化タンタル層であるが、PDV法で蒸着される。
− アルミニウム170のパターニングのためのリソグラフィ法を実行し、端子板180と、最上部電極182と、上部端子ライン184と、ブロックコンデンサ114の上部板と、ヒューズ部186との位置が決められる。コイルまたは、信号を担うための接続の位置についてもさらに決められる。
− アルミニウム170がエッチングされ、中間層160の上部エリアで停止する。
− フォトレジストが除去され、洗浄段階が実行される。
最終不動態化:
− 二酸化珪素190または他の適切な材料、例えばFSGが蒸着される。それに引き続いて窒化物層199が蒸着される。
− カットアウト196と202の位置を決めるため、リソグラフィ法を実施する。これらの開口部はそれぞれ端子板180とヒューズ部186にそれぞれつながる。
− カットアウト196と202をエッチングする。
− フォトレジストが除去され、洗浄段階が実行される。
下部金属層106a,108a,102aの作製:
− 図2に関する説明に対して参照する。
中間層304の作製に対する変形例:
d),e)中間層160作製のための変形例dとeを参照のこと。
− 二酸化珪素316または他の適切な材料、例えばFSGを蒸着させる。
− 接触開口部303,164a,166aの位置を決めるため、リソグラフィ法を実行する。
− 接触穴303,164a,166aの後の位置より上の二酸化珪素316内に接触穴がエッチングされる。中間層304でエッチング作業を停止する。
− フォトレジスト層が除去される。
− 銅148aの覆いが取られるまで、中間層304を通して接触穴がエッチングされる。
金属層104a内トレンチの作製:
− 銅312が導入されるトレンチの位置を決めるため、リソグラフィ法を実行する。
− トレンチのエッチングを行い、中間層304で停止する。この場合、端子板306、最上部電極308、作動電圧ライン184、端子部310に対するトレンチが作製される。さらに、同時に、ブロックキャパシタンスをもつ作動電圧ライン、信号ライン、またはコイルに対するトレンチが作製可能である。
− フォトレジスト層が除去される。
− 接触穴の底部に作製された可能性のある酸化銅を除去するため、例えば、湿式洗浄段階(例えば、EKC525)で接触穴を洗浄する。
金属層104aの追加作製:
− バリア層314を蒸着させ、この場合、(例えばH2に基づく)スパッタリング前洗浄または反応性前洗浄を行う。例えば、PVD法またはCVD法でバリア蒸着が行われる。バリア層172に対して、同一の材料を用いることが可能である。
− 例えば、PVD法またはCDV法、もしくは溶液からの無電解法により成長核を持つ銅層が引き続いて蒸着される。
− 二重ダマシン充填法、例えばECD法(電気化学蒸着)により銅312が導入される。
− CMP法によりトレンチ外にある銅312とバリア層314が除去される。
− バリア層318が施工される。バリア層318は約20nm〜約30nmの厚さをもつ。例として、PECVD法またはHDP法により窒化珪素が施工される。しかし、他の方法、例えば低誘電率kのバリア材料(ブロック−バリア低k)を用いることも可能である。
− 引き続いて、例えば二酸化珪素層320や窒化珪素層194aの施工により不動態化が作製される。
− カットアウト196aと202aの位置を決めるため、リソグラフィ法を実行する。
− カットアウト196aと202aのエッチングを行い、バリア層318で停止する。
− フォトレジスト層が除去される。
− カットアウト196aと202aの領域を通して、バリア層318のエッチングを行う。
− 極端に薄いが高密度の誘電体層322の蒸着を行うが、これは例えば5nmの厚さをもつ。例えば、ALCVD法(原子層CVD)を用いて蒸着を行う。適した材料は窒化珪素である。誘電体層322は、腐食や酸化に対して銅端子板206やヒューズ部310を防護する。しかし、誘電体層322は、Cu端子板306に対してボンディングが決して影響を与えないほど十分薄くなければならない。
下部金属層106b,108b,102bの作製:
− 図2に関する説明に対して参照する。
− 20nm超の厚さをもつバリア層402は、例えばPECVD法またはHDP法により平準金属層102に蒸着される。バリア層402は、例えば、窒化珪素または低誘電率k材料(ブロック)、例えば炭化珪素を含む。
− 酸化物層、例えば二酸化珪素404をバリア層402に蒸着させる。代替法として、別の材料、例えばFSGを用いることも可能である。
− 銅312bが引き続いて導入されるトレンチの位置を決めるため、リソグラフィ法を実行する。
− トレンチのエッチングを行い、バリア層402で停止する。
− 銅の酸化を防ぐため、フォトレジストを除去する。
− トレンチの領域を通して、バリア層402のエッチングを行う。銅148bより上部のバリア層402の領域を確実に完全に除去するため、オーバーエッチングさせなければならない。これにより、銅よりも二酸化珪素152bのある領域、すなわちボンディング接続110bよりも下部の領域でヒューズ接続116bよりも下部の領域で深いトレンチが得られる。
中間層400の作製に対する変形例:
d),e)中間層160作製のための変形例dとeをそれぞれ参照のこと。
接触穴作製(バイア)の作製:
− 接触穴303b,164b,166bと追加接触穴(図示されていない)の位置は、リソグラフィ法により決められる。
−接触穴を金属間層400内にエッチングする。
− フォトレジスト層が除去される。
− 接触穴の底部に作製された可能性のある酸化銅を除去するため、例えば、湿式洗浄段階(EKC525)で接触穴を洗浄する。
− 金属層104aの追加作製に関連して、図3についての説明に対して参照を行う。CMP法を実行する場合、銅312bとバリア層314bに追加して、トレンチ外の中間層400も除去されるという点だけが異なる。
すでに述べた本発明、開発例、代表的実施例の利点に加えて、以下の点にも注目すべきである:
− 最上部アルミニウム板は比較的厚く広い作動電圧ラインに対して利用可能である。接触穴(バイア)中にタングステン充填を行うことなくアルミニウムから配線面を作製することは、CMP法で銅平面を作製することよりさらに費用効果が大きい。末端金属面を平坦化する必要がないため、銅面は必要ない。
− リソグラフィでの要求事項が比較的緩和されているため、端末アルミニウム面のパターン化に対して既存の装置が利用できる。
− 最端の2つの金属層、例えば、低インピーダンス給電ライン(ラインアウト)または特に感度の高い混合信号ライン内で信号を担うことが可能である。容量的に強力結合された2つの金属層内に信号ラインが配置されている場合、確実に信号層がお互い交差しないよう注意を払う必要がある。しかし代替法として、信号ラインを平行な2平面内にひいて、それにより特に低インピーダンス信号ラインを使用可能にするということもできる。これに対する追加支出は低い。理由は、必ず必要なことが追加の配置面を準備することだけであり、これはソフトウェア技術で達成可能なためである。
− 端末金属層または前端末金属層内の信号ライン間の最小距離を、例えば10から20%に若干広げることにより、2面のうち1つの面内の信号ライン間の容量結合が強くなることを防ぐことができる。
Claims (19)
- 集積回路装置10,100であって、
半導体基板12に配置された構成部品をもち、
2つの接続層102,104をもち、各層が、構成部品に対する導電接続の一部となる少なくとも1つの導電接続部148,170を含み、
少なくとも1つの誘電体材料でできた中間層160,400をもち、この中間層が接続層102,104間に配置されているものであって、
中間層160,400が接続層102,104間の単位面積当たりキャパシタンスを決め、
接続層102,104間の単位面積当たりキャパシタンスが0.5fF/μm2超または0.7fF/μm2超または約2.0fF/μm2となるよう中間層160,400が設計されることを特徴とする回路装置。 - 請求項1に記載の回路装置10,100であって、回路装置10,100が周囲影響に対する防護のための不活性化層194を含み、
接続層104の接続部180につながる少なくとも1つのカットアウト196を不活性化層194が含み、
外部導電接続部200を接続するための端子を接続部180が形成することを特徴とする回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、回路装置10,100が周囲影響に対する防護のための不活性化層194を含み、
接続層104の接続部186につながる少なくとも1つのカットアウト202を不活性化層194が含み、
接続部186が、少なくとも2つの回路可変要素のうちの1つを選択する、あるいは選択したことによるヒューズ接続であることを特徴とする回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、作動電圧を担うため、1つの接続層104の少なくとも1つの接続部184と他の接続層102の少なくとも1つの接続部142を用意し、
接続部184,142が、接続層102,104に対して垂直に見えるよう、回路装置10,100の作動中に発生する干渉パルスを抑制するコンデンサC2,C3を形成する領域で重なることを特徴とするものであって、
好ましくは、接続部184,142が、デジタル信号で作動する回路装置10,100の回路部16に配置されている回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、接続層102,104が、少なくとも1つのコンデンサC1,72の電極149,182を含み、
コンデンサC1,72の領域の中間層160,400の一部が誘電体を形成することを特徴とするものであって、
好ましくは、コンデンサC1,72が、アナログ信号で作動する回路装置10,100の回路部14に配置されている回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、接続層102,104に対して垂直に見えるよう重なり、中間層において、接続、特に細長穴接続によりお互いに接続された導電領域を接続層102,104が含むことを特徴とするものであって、
好ましくは、導電領域がらせんコースをもち、
導電領域が、回路の機能を確保するインダクタンスを形成する回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、4より大きい、または6より大きい、好ましくは30より小さい誘電率をもつ少なくとも1つの材料を中間層106,400が含み、
および/または、材料が、異なる接続層102,104の相互に逆方向の導電領域140,182;148,184間の空間を好ましくは実質的に完全に満たし、
および/または、接続層102,104は、お互いに200nm未満または150nm未満、好ましくは約100nmの距離をもつことを特徴とする回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、両接続層102,104が、主構成要素と同一の材料を含み、
あるいは、1つの接続層102が、他の接続層104の主構成要素を形成する材料と異なる主構成要素となる材料を含むことを特徴とするものであって、
材料が好ましくは、アルミニウム、アルミニウム合金、銅、もしくは銅合金である回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、2つの接続層102,104のうち最後に施工された接続層104が、主構成要素としてアルミニウムまたはアルミニウム合金を含み、
接続層102,104間の接触穴162が同様にアルミニウムまたはアルミニウム合金で充填されていることを特徴とする回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、中間層160,400が少なくとも1つの窒化物構成要素、好ましくは、窒化珪素または窒化アルミニウム、酸化タンタル、酸化ハフニウムまたは酸化アルミニウムを含むことを特徴とする回路装置。
- 前記請求項の1つに記載の回路装置10,100であって、中間層160,400が、異なる処理条件下で作製された少なくとも2つの層を含むことを特徴とするものであって、
好ましくは1つの層が始めにHDP法で作製され、1つの層がその後にPECVD法で作製され、
初めに作製された層が、後で作製された層と同一の材料を主構成要素として含み、
あるいは、初めに作製された層が、後で作製された層と異なる材料を主構成要素として含む回路装置。 - 請求項11に記載の回路装置10,100であって、2つの層のうちの少なくとも1つが、特定の処理条件下において材料の蒸着の中断により、さらに同一の処理条件下において同一材料の蒸着の継続により作製された多層堆積であることを特徴とする回路装置。
- 前記請求項の1つに記載の回路装置10,100であって、最初に作製された接続層102が、主構成要素として銅または銅合金を含み、
補助層が第1の接続層102と中間層160,400間に配置され、この補助層が、第1の接続層102の接続部148において、銅および、コバルト、タングステン、燐またはホウ素の中の少なくとも1つの材料とを含む銅化合物を主に含む領域を含むことを特徴とする回路装置。 - 前記請求項の1つに記載の回路装置10,100であって、回路装置10,100がさらに接続層20〜30を含み、
単位面積当たりキャパシタンスの高い接続層32,34が、基板12から最も遠くに配置された接続層20〜34であることを特徴とする回路装置。 - 特に、前記請求項の1つに記載の集積回路装置10,100を作製するための方法であって、
電子構成部品が半導体基板12中に作製され、
構成部品の作製後に、接続層102が施工され、この接続層が接続層構成部品に対する導電接続の一部となる少なくとも1つの導電接続部148を含み、
接続層102の施工後に、少なくとも1つの誘電体材料でできた中間層160が施工され、
中間層160の施工後に、上部接続層104が施工され、この接続層が構成部品に対する導電接続の一部となる少なくとも1つの導電接続部170を含み、
接続層102,104間の単位面積当たりのキャパシタンスが0.5fF/μm2超または0.7fF/μm2超または約2.0fF/μm2となるよう中間層160が設計されることを特徴とする方法。 - 請求項15に記載の方法であって、上部接続層104の作製が開始される前に中間層160が施工され、
または、上部接続層316の接続部312に対するカットアウト中に中間層400が蒸着されることを特徴とする方法。 - 特に、請求項1〜14の1つに記載の集積回路装置を作製するための方法であって、
好ましくは、銅または銅合金でできた金属層148がキャリヤ材料152上に施工され、
金属層148の施工後に、中間層160,400が施工され、この中間層が、異なる処理条件下で作製された少なくとも2つの層を含み、
最初に作製された層がHDP法で蒸着され、その後作製された層がPECVD法で蒸着されることを特徴とする方法であって、
最初に作製された層が、後に作製された層と同一の材料を主構成要素として含む、または最初に作製された層が、後に作製された層と異なる材料を主構成要素として含む方法。 - 請求項17に記載の方法であって、2つの層のうちの少なくとも1つが、材料の蒸着の重複中断により、さらに同一の処理条件下において同一材料の蒸着の継続により作製されたことを特徴とする方法。
- 特に、請求項1〜14の1つに記載の集積回路装置を作製するための方法であって、
好ましくは、銅または銅合金でできた金属層148がキャリヤ材料上に施工され、
金属層の施工後に、補助層が施工され、この補助層が、銅と、コバルト、タングステン、燐またはホウ素の少なくとも1つとを含む銅化合物を主に含み、
接続層の施工後に、誘電体材料でできた中間層が施工されることを特徴とする方法。
全ての代表的実施例において、回路装置は、接続層間の0.5fF/μm2超または0.7fF/μm2超または約2fF/μm2の単位面積当たりキャパシタンスを決める中間層を通してのみ貫通する少なくとも1つの接触穴を含む。言い換えると、前記単位面積当たりキャパシタンスを決める中間層から離れた層を通して接触穴は貫通しない。
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