JP2005526399A - 厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法 - Google Patents

厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法 Download PDF

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Publication number
JP2005526399A
JP2005526399A JP2004506080A JP2004506080A JP2005526399A JP 2005526399 A JP2005526399 A JP 2005526399A JP 2004506080 A JP2004506080 A JP 2004506080A JP 2004506080 A JP2004506080 A JP 2004506080A JP 2005526399 A JP2005526399 A JP 2005526399A
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JP
Japan
Prior art keywords
substrate
gate insulating
layer
fluorine
implanted
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Pending
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JP2004506080A
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English (en)
Japanese (ja)
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JP2005526399A5 (https=
Inventor
エフ． ビューラー ジェイムズ
ディー． チーク ジョン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2005526399A publication Critical patent/JP2005526399A/ja
Publication of JP2005526399A5 publication Critical patent/JP2005526399A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
JP2004506080A 2002-05-14 2002-12-17 厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法 Pending JP2005526399A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/145,519 US6541321B1 (en) 2002-05-14 2002-05-14 Method of making transistors with gate insulation layers of differing thickness
PCT/US2002/040500 WO2003098685A1 (en) 2002-05-14 2002-12-17 Method of making transistors with gate insulation layers of differing thickness

Publications (2)

Publication Number Publication Date
JP2005526399A true JP2005526399A (ja) 2005-09-02
JP2005526399A5 JP2005526399A5 (https=) 2006-02-16

Family

ID=22513473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004506080A Pending JP2005526399A (ja) 2002-05-14 2002-12-17 厚みの異なる複数のゲート絶縁層を備えたトランジスタを形成するための方法

Country Status (7)

Country Link
US (1) US6541321B1 (https=)
EP (1) EP1504470A1 (https=)
JP (1) JP2005526399A (https=)
KR (1) KR100940352B1 (https=)
CN (1) CN1310314C (https=)
AU (1) AU2002353166A1 (https=)
WO (1) WO2003098685A1 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004519090A (ja) * 2000-08-07 2004-06-24 アンバーウェーブ システムズ コーポレイション 歪み表面チャネル及び歪み埋め込みチャネルｍｏｓｆｅｔ素子のゲート技術
AU2002322105A1 (en) * 2001-06-14 2003-01-02 Amberware Systems Corporation Method of selective removal of sige alloys
AU2003201110A1 (en) * 2002-02-01 2003-09-02 Koninklijke Philips Electronics N.V. Method for forming high quality oxide layers of different thickness in one processing step
US6879007B2 (en) * 2002-08-08 2005-04-12 Sharp Kabushiki Kaisha Low volt/high volt transistor
CN100521071C (zh) * 2003-07-11 2009-07-29 Nxp股份有限公司 一种半导体器件的制造方法及在这种方法中使用的装置
JP2007519222A (ja) * 2003-07-11 2007-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体デバイスを製造する方法およびその方法で使用するための装置
US20050112824A1 (en) * 2003-11-26 2005-05-26 Yu-Chang Jong Method of forming gate oxide layers with multiple thicknesses on substrate
JP4040602B2 (ja) * 2004-05-14 2008-01-30 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2006344634A (ja) * 2005-06-07 2006-12-21 Renesas Technology Corp Ｃｍｏｓ型半導体装置の製造方法および、ｃｍｏｓ型半導体装置
US7410874B2 (en) * 2006-07-05 2008-08-12 Chartered Semiconductor Manufacturing, Ltd. Method of integrating triple gate oxide thickness
KR100853796B1 (ko) * 2007-06-07 2008-08-25 주식회사 동부하이텍 반도체 소자의 제조 방법
US20090065820A1 (en) * 2007-09-06 2009-03-12 Lu-Yang Kao Method and structure for simultaneously fabricating selective film and spacer
US8232605B2 (en) * 2008-12-17 2012-07-31 United Microelectronics Corp. Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
US8828834B2 (en) 2012-06-12 2014-09-09 Globalfoundries Inc. Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
US8975143B2 (en) 2013-04-29 2015-03-10 Freescale Semiconductor, Inc. Selective gate oxide properties adjustment using fluorine
US9263270B2 (en) 2013-06-06 2016-02-16 Globalfoundries Inc. Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structure
US12532464B2 (en) 2021-08-19 2026-01-20 Sk Keyfoundry Inc. Semiconductor device including single poly non-volatile memory device and method of manufacturing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0136935B1 (ko) * 1994-04-21 1998-04-24 문정환 메모리 소자의 제조방법
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
JP3194370B2 (ja) * 1998-05-11 2001-07-30 日本電気株式会社 半導体装置とその製造方法
JP2000003965A (ja) * 1998-06-15 2000-01-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6335262B1 (en) * 1999-01-14 2002-01-01 International Business Machines Corporation Method for fabricating different gate oxide thicknesses within the same chip
US6251747B1 (en) * 1999-11-02 2001-06-26 Philips Semiconductors, Inc. Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

Also Published As

Publication number Publication date
CN1625803A (zh) 2005-06-08
CN1310314C (zh) 2007-04-11
KR20040106546A (ko) 2004-12-17
AU2002353166A1 (en) 2003-12-02
KR100940352B1 (ko) 2010-02-04
EP1504470A1 (en) 2005-02-09
WO2003098685A1 (en) 2003-11-27
US6541321B1 (en) 2003-04-01

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