JP2005510081A - 低エネルギープラズマ強化化学蒸着法による高移動度のシリコンゲルマニウム構造体の製造方法 - Google Patents
低エネルギープラズマ強化化学蒸着法による高移動度のシリコンゲルマニウム構造体の製造方法 Download PDFInfo
- Publication number
- JP2005510081A JP2005510081A JP2003546385A JP2003546385A JP2005510081A JP 2005510081 A JP2005510081 A JP 2005510081A JP 2003546385 A JP2003546385 A JP 2003546385A JP 2003546385 A JP2003546385 A JP 2003546385A JP 2005510081 A JP2005510081 A JP 2005510081A
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- growth
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- lepecvd
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3204—Materials thereof being Group IVA semiconducting materials
- H10P14/3211—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
- H10P14/3248—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3242—Structure
- H10P14/3244—Layer structure
- H10P14/3254—Graded layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3411—Silicon, silicon germanium or germanium
Landscapes
- Chemical Vapour Deposition (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP01127834A EP1315199A1 (en) | 2001-11-22 | 2001-11-22 | Formation of high-mobility silicon-germanium structures by low-energy plasma enhanced chemical vapor deposition |
| PCT/EP2002/009922 WO2003044839A2 (en) | 2001-11-22 | 2002-09-05 | Formation of high-mobility silicon-germanium structures by low-energy plasma enhanced chemical vapor deposition |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005510081A true JP2005510081A (ja) | 2005-04-14 |
| JP2005510081A5 JP2005510081A5 (https=) | 2006-01-05 |
Family
ID=8179316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003546385A Pending JP2005510081A (ja) | 2001-11-22 | 2002-09-05 | 低エネルギープラズマ強化化学蒸着法による高移動度のシリコンゲルマニウム構造体の製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7115895B2 (https=) |
| EP (1) | EP1315199A1 (https=) |
| JP (1) | JP2005510081A (https=) |
| CN (1) | CN100345254C (https=) |
| AU (1) | AU2002335310A1 (https=) |
| WO (1) | WO2003044839A2 (https=) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010267969A (ja) * | 2009-05-13 | 2010-11-25 | Siltronic Ag | おもて面と裏面とを有するシリコン単結晶基板及び前記おもて面上に堆積されたSiGeの層を含んでなるウェーハを製造する方法 |
| KR20140147250A (ko) * | 2013-06-19 | 2014-12-30 | 엘지이노텍 주식회사 | 반도체 기판, 발광 소자 및 전자 소자 |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6855436B2 (en) * | 2003-05-30 | 2005-02-15 | International Business Machines Corporation | Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal |
| US7678645B2 (en) | 2003-03-26 | 2010-03-16 | Eidgenoessische Technische Hochschule Zuerich | Formation of thin semiconductor layers by low-energy plasma enhanced chemical vapor deposition and semiconductor heterostructure devices |
| EP1513233B1 (en) * | 2003-09-05 | 2008-10-29 | Epispeed S.A. | InGaAs/GaAs lasers on Silicon produced by LEPECVD and MOCVD |
| DE602005027196D1 (de) | 2004-04-30 | 2011-05-12 | Dichroic Cell S R L | Verfahren zur herstellung von virtuellen ge-substraten zur iii/v-integration auf si(001) |
| JP2007250903A (ja) * | 2006-03-16 | 2007-09-27 | Matsushita Electric Ind Co Ltd | ヘテロ接合バイポーラトランジスタおよびその製造方法 |
| EP2049939A1 (en) * | 2006-08-11 | 2009-04-22 | Paul Scherrer Institut | Light modulators comprising si-ge quantum well layers |
| US8535060B2 (en) | 2006-08-25 | 2013-09-17 | Brain & Science Llc | System and method for detecting a specific cognitive-emotional state in a subject |
| FR2914783A1 (fr) * | 2007-04-03 | 2008-10-10 | St Microelectronics Sa | Procede de fabrication d'un dispositif a gradient de concentration et dispositif correspondant. |
| US8237126B2 (en) * | 2007-08-17 | 2012-08-07 | Csem Centre Suisse D'electronique Et De Mictrotechnique Sa | X-ray imaging device and method for the manufacturing thereof |
| EP2207911A1 (en) * | 2007-08-17 | 2010-07-21 | Epispeed S.A. | Apparatus and method for producing epitaxial layers |
| TWI562195B (en) | 2010-04-27 | 2016-12-11 | Pilegrowth Tech S R L | Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication |
| CN103165420B (zh) * | 2011-12-14 | 2015-11-18 | 中国科学院上海微系统与信息技术研究所 | 一种SiGe中嵌入超晶格制备应变Si的方法 |
| CN105632927B (zh) * | 2014-10-30 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管的形成方法 |
| KR102465536B1 (ko) * | 2016-06-08 | 2022-11-14 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
| US20260033255A1 (en) * | 2024-07-23 | 2026-01-29 | Samsung Electronics Co., Ltd. | Deposition by electron enhanced processes with positive substrate voltage |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0380077A3 (en) * | 1989-01-25 | 1990-09-12 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
| US5241197A (en) * | 1989-01-25 | 1993-08-31 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
| US5442205A (en) * | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
| MY127672A (en) * | 1999-03-12 | 2006-12-29 | Ibm | High speed ge channel heterostructures for field effect devices |
-
2001
- 2001-11-22 EP EP01127834A patent/EP1315199A1/en not_active Withdrawn
-
2002
- 2002-09-05 CN CNB028273095A patent/CN100345254C/zh not_active Expired - Fee Related
- 2002-09-05 AU AU2002335310A patent/AU2002335310A1/en not_active Abandoned
- 2002-09-05 WO PCT/EP2002/009922 patent/WO2003044839A2/en not_active Ceased
- 2002-09-05 JP JP2003546385A patent/JP2005510081A/ja active Pending
- 2002-09-05 US US10/496,245 patent/US7115895B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010267969A (ja) * | 2009-05-13 | 2010-11-25 | Siltronic Ag | おもて面と裏面とを有するシリコン単結晶基板及び前記おもて面上に堆積されたSiGeの層を含んでなるウェーハを製造する方法 |
| KR20140147250A (ko) * | 2013-06-19 | 2014-12-30 | 엘지이노텍 주식회사 | 반도체 기판, 발광 소자 및 전자 소자 |
| KR102142707B1 (ko) * | 2013-06-19 | 2020-08-07 | 엘지이노텍 주식회사 | 반도체 기판, 발광 소자 및 전자 소자 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100345254C (zh) | 2007-10-24 |
| US7115895B2 (en) | 2006-10-03 |
| AU2002335310A1 (en) | 2003-06-10 |
| CN1615540A (zh) | 2005-05-11 |
| EP1315199A1 (en) | 2003-05-28 |
| AU2002335310A8 (en) | 2003-06-10 |
| WO2003044839A2 (en) | 2003-05-30 |
| US20050116226A1 (en) | 2005-06-02 |
| WO2003044839A3 (en) | 2003-10-30 |
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