JP2005503004A5 - - Google Patents

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Publication number
JP2005503004A5
JP2005503004A5 JP2003504222A JP2003504222A JP2005503004A5 JP 2005503004 A5 JP2005503004 A5 JP 2005503004A5 JP 2003504222 A JP2003504222 A JP 2003504222A JP 2003504222 A JP2003504222 A JP 2003504222A JP 2005503004 A5 JP2005503004 A5 JP 2005503004A5
Authority
JP
Japan
Prior art keywords
transmission line
clock distribution
signal
integrated circuit
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003504222A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005503004A (ja
JP4886164B2 (ja
Filing date
Publication date
Priority claimed from US10/113,052 external-priority patent/US6667647B2/en
Application filed filed Critical
Publication of JP2005503004A publication Critical patent/JP2005503004A/ja
Publication of JP2005503004A5 publication Critical patent/JP2005503004A5/ja
Application granted granted Critical
Publication of JP4886164B2 publication Critical patent/JP4886164B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2003504222A 2001-06-13 2002-06-12 低電力クロック分配方法 Expired - Lifetime JP4886164B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29794001P 2001-06-13 2001-06-13
US60/297,940 2001-06-13
US10/113,052 US6667647B2 (en) 2001-06-13 2002-04-01 Low power clock distribution methodology
US10/113,052 2002-04-01
PCT/US2002/018673 WO2002101527A1 (en) 2001-06-13 2002-06-12 Low power clock distribution methodology

Publications (3)

Publication Number Publication Date
JP2005503004A JP2005503004A (ja) 2005-01-27
JP2005503004A5 true JP2005503004A5 (https=) 2005-08-04
JP4886164B2 JP4886164B2 (ja) 2012-02-29

Family

ID=26810660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003504222A Expired - Lifetime JP4886164B2 (ja) 2001-06-13 2002-06-12 低電力クロック分配方法

Country Status (6)

Country Link
US (1) US6667647B2 (https=)
EP (1) EP1395894A4 (https=)
JP (1) JP4886164B2 (https=)
KR (1) KR100588802B1 (https=)
CN (1) CN1267803C (https=)
WO (1) WO2002101527A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
JP4457613B2 (ja) * 2003-09-04 2010-04-28 ソニー株式会社 固体撮像装置
US7446622B2 (en) * 2003-09-05 2008-11-04 Infinera Corporation Transmission line with low dispersive properties and its application in equalization
US7109902B2 (en) * 2004-06-30 2006-09-19 Texas Instruments Incorporated Method and system for sampling a signal
KR100808076B1 (ko) * 2005-09-16 2008-03-03 후지쯔 가부시끼가이샤 클록 분배 회로
US20070229115A1 (en) * 2006-01-25 2007-10-04 International Business Machines Corporation Method and apparatus for correcting duty cycle error in a clock distribution network
WO2014039817A2 (en) 2012-09-07 2014-03-13 Calhoun Benton H Low power clock source
US20150033050A1 (en) * 2013-07-25 2015-01-29 Samsung Electronics Co., Ltd Semiconductor integrated circuit and computing device including the same
US11579649B1 (en) 2021-12-30 2023-02-14 Analog Devices, Inc. Apparatus and methods for clock duty cycle correction and deskew

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934032B2 (ja) * 1980-03-06 1984-08-20 日本原子力事業株式会社 信号伝送線路におけるリンギング防止回路
JP2665517B2 (ja) * 1989-09-29 1997-10-22 株式会社日立製作所 終端回路
JPH03186020A (ja) * 1989-12-15 1991-08-14 Mitsubishi Electric Corp 終端回路
DE69125816T2 (de) * 1991-02-21 1997-10-23 Ibm DÜE und Verfahren zur Bearbeitung von DÜE empfangener Daten zum Einsatz verschiedener Betriebsarten
EP0542321A3 (en) * 1991-09-23 1993-06-09 Schlumberger Technologies, Inc. Method and circuit for controlling voltage reflections on transmission lines
JPH05143535A (ja) * 1991-10-18 1993-06-11 Toshiba Corp 半導体集積回路
JPH06332569A (ja) * 1993-05-26 1994-12-02 Nippon Telegr & Teleph Corp <Ntt> 実時間タイマ一致化装置および一致方法
JP2735034B2 (ja) 1995-06-14 1998-04-02 日本電気株式会社 クロック信号分配回路
US5911063A (en) 1996-07-10 1999-06-08 International Business Machines Corporation Method and apparatus for single phase clock distribution with minimal clock skew
JP3441948B2 (ja) 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
JP2000200114A (ja) * 1999-01-07 2000-07-18 Nec Corp クロック分配回路
US6249193B1 (en) * 1999-02-23 2001-06-19 International Business Machines Corporation Termination impedance independent system for impedance matching in high speed input-output chip interfacing

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