JP2005318630A5 - - Google Patents

Download PDF

Info

Publication number
JP2005318630A5
JP2005318630A5 JP2005131471A JP2005131471A JP2005318630A5 JP 2005318630 A5 JP2005318630 A5 JP 2005318630A5 JP 2005131471 A JP2005131471 A JP 2005131471A JP 2005131471 A JP2005131471 A JP 2005131471A JP 2005318630 A5 JP2005318630 A5 JP 2005318630A5
Authority
JP
Japan
Prior art keywords
signal
digital
pattern
error rate
bit error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005131471A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005318630A (ja
Filing date
Publication date
Priority claimed from US10/836,178 external-priority patent/US7609758B2/en
Application filed filed Critical
Publication of JP2005318630A publication Critical patent/JP2005318630A/ja
Publication of JP2005318630A5 publication Critical patent/JP2005318630A5/ja
Pending legal-status Critical Current

Links

JP2005131471A 2004-04-30 2005-04-28 ディジタル信号パターンにおけるビット移相方法 Pending JP2005318630A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/836,178 US7609758B2 (en) 2004-04-30 2004-04-30 Method of phase shifting bits in a digital signal pattern

Publications (2)

Publication Number Publication Date
JP2005318630A JP2005318630A (ja) 2005-11-10
JP2005318630A5 true JP2005318630A5 (enExample) 2007-09-06

Family

ID=35187106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005131471A Pending JP2005318630A (ja) 2004-04-30 2005-04-28 ディジタル信号パターンにおけるビット移相方法

Country Status (2)

Country Link
US (1) US7609758B2 (enExample)
JP (1) JP2005318630A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7239969B2 (en) * 2004-11-09 2007-07-03 Guide Technology, Inc. System and method of generating test signals with injected data-dependent jitter (DDJ)
US7400988B2 (en) 2004-12-08 2008-07-15 Guide Technology, Inc. Periodic jitter (PJ) measurement methodology
US8255188B2 (en) * 2007-11-07 2012-08-28 Guidetech, Inc. Fast low frequency jitter rejection methodology
US7843771B2 (en) * 2007-12-14 2010-11-30 Guide Technology, Inc. High resolution time interpolator
US7944963B2 (en) * 2007-12-28 2011-05-17 International Business Machines Corporation Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern
US10771076B1 (en) * 2019-03-27 2020-09-08 Rohde & Schwarz Gmbh & Co. Kg Measuring device, calibration method and measuring method with jitter compensation

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859972A (en) * 1988-11-01 1989-08-22 The Board Of Trustees Of The University Of Illinois Continuous phase shifter for a phased array hyperthermia system
GB2248356A (en) * 1990-09-28 1992-04-01 Philips Electronic Associated Analogue-to-digital converter
JP2710525B2 (ja) * 1992-11-05 1998-02-10 株式会社フジクラ ジッタ抑制回路
GB9313020D0 (en) * 1993-06-24 1993-08-11 Madge Networks Ltd Jitter monitoring
US5479457A (en) * 1993-08-27 1995-12-26 Vlsi Technology Inc. Method and apparatus for attenuating jitter in a digital transmission line
US5856804A (en) * 1996-10-30 1999-01-05 Motorola, Inc. Method and intelligent digital beam forming system with improved signal quality communications
US6076175A (en) * 1997-03-31 2000-06-13 Sun Microsystems, Inc. Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
JPH11308282A (ja) * 1998-04-20 1999-11-05 Fuji Electric Co Ltd フィールドバス伝送信号のジッタ補正回路
JP2000183992A (ja) * 1998-12-18 2000-06-30 Toshiba Corp クロック再生方法および回路
JP2002217258A (ja) * 2001-01-22 2002-08-02 Hitachi Ltd 半導体装置およびその測定方法、ならびに半導体装置の製造方法
JP3950646B2 (ja) * 2001-05-21 2007-08-01 株式会社日立製作所 負荷電流出力回路一体形ドライバ回路及、それを備えたピンエレクトロニクスｉｃ及びｉｃテスタ
US6625560B1 (en) * 2001-07-13 2003-09-23 Silicon Image, Inc. Method of testing serial interface
US6847247B2 (en) * 2001-11-27 2005-01-25 Sun Microsystems, Inc. Jittery polyphase clock
US6885209B2 (en) * 2002-08-21 2005-04-26 Intel Corporation Device testing
US7047457B1 (en) * 2003-09-11 2006-05-16 Xilinx, Inc. Testing of a multi-gigabit transceiver
WO2005060655A2 (en) * 2003-12-16 2005-07-07 California Institute Of Technology Deterministic jitter equalizer

Similar Documents

Publication Publication Date Title
DE602006021305D1 (de) Musterabhängiger phasendetektor zur taktwiedergewinnung
JP5416279B2 (ja) 試験装置および試験方法
CN101799705B (zh) 一种高速dds信号发生器
WO2008112153A3 (en) Variable instruction width software programmable data pattern generator
US7409005B2 (en) High speed data transmitter and transmitting method thereof
ATE398308T1 (de) Serielle verbindungsarchitektur
JP2002243805A5 (enExample)
US20080129561A1 (en) Multiplexer for controlling data output sequence and parallel-to-serial converter using the same
WO2009069205A1 (ja) ビット識別回路
JP2004523056A5 (enExample)
JP2005318630A5 (enExample)
WO2007019339A3 (en) Clock-and-data-recovery system
WO2003073244A3 (en) Frequency divider
JP2003032084A (ja) 入出力インタフェースおよび半導体集積回路
JP2006145527A5 (enExample)
JP2005233933A (ja) 組合せ試験方法及び試験装置
CN102843127A (zh) 用于捷变信号控制的数字数据延迟方法
KR101633542B1 (ko) 저전력 광대역 송신기를 위한 위상 보간기에 근거하는 출력 파형 합성 장치
TW200510987A (en) Method and related apparatus for outputting clock through data path
TW200514399A (en) Clock and data recovery circuit
US7653758B2 (en) Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock signals are applied in parallel
JP2004222296A5 (enExample)
JP2006333272A (ja) データ・パターン発生装置
WO2006075206A3 (en) Digital clock dividing circuit
JP2004242304A5 (enExample)