JP2005318630A - ディジタル信号パターンにおけるビット移相方法 - Google Patents

ディジタル信号パターンにおけるビット移相方法 Download PDF

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Publication number
JP2005318630A
JP2005318630A JP2005131471A JP2005131471A JP2005318630A JP 2005318630 A JP2005318630 A JP 2005318630A JP 2005131471 A JP2005131471 A JP 2005131471A JP 2005131471 A JP2005131471 A JP 2005131471A JP 2005318630 A JP2005318630 A JP 2005318630A
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Japan
Prior art keywords
digital
signal
pattern
bit
jitter
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Pending
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JP2005131471A
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English (en)
Japanese (ja)
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JP2005318630A5 (enExample
Inventor
Roger L Jungerman
ロジャー・エル・ジャンガーマン
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Agilent Technologies Inc
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Agilent Technologies Inc
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Publication of JP2005318630A publication Critical patent/JP2005318630A/ja
Publication of JP2005318630A5 publication Critical patent/JP2005318630A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring

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  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Networks Using Active Elements (AREA)
JP2005131471A 2004-04-30 2005-04-28 ディジタル信号パターンにおけるビット移相方法 Pending JP2005318630A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/836,178 US7609758B2 (en) 2004-04-30 2004-04-30 Method of phase shifting bits in a digital signal pattern

Publications (2)

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JP2005318630A true JP2005318630A (ja) 2005-11-10
JP2005318630A5 JP2005318630A5 (enExample) 2007-09-06

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ID=35187106

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JP2005131471A Pending JP2005318630A (ja) 2004-04-30 2005-04-28 ディジタル信号パターンにおけるビット移相方法

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US (1) US7609758B2 (enExample)
JP (1) JP2005318630A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7239969B2 (en) * 2004-11-09 2007-07-03 Guide Technology, Inc. System and method of generating test signals with injected data-dependent jitter (DDJ)
WO2006063361A2 (en) 2004-12-08 2006-06-15 Guide Technology Periodic jitter (pj) measurement methodology
US8255188B2 (en) * 2007-11-07 2012-08-28 Guidetech, Inc. Fast low frequency jitter rejection methodology
US7843771B2 (en) * 2007-12-14 2010-11-30 Guide Technology, Inc. High resolution time interpolator
US7944963B2 (en) * 2007-12-28 2011-05-17 International Business Machines Corporation Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern
US10771076B1 (en) * 2019-03-27 2020-09-08 Rohde & Schwarz Gmbh & Co. Kg Measuring device, calibration method and measuring method with jitter compensation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152579A (ja) * 1992-11-05 1994-05-31 Fujikura Ltd ジッタ抑制回路
JPH11308282A (ja) * 1998-04-20 1999-11-05 Fuji Electric Co Ltd フィールドバス伝送信号のジッタ補正回路
JP2000183992A (ja) * 1998-12-18 2000-06-30 Toshiba Corp クロック再生方法および回路
JP2002340985A (ja) * 2001-05-21 2002-11-27 Hitachi Ltd 負荷電流出力回路一体形ドライバ回路及、それを備えたピンエレクトロニクスｉｃ及びｉｃテスタ

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859972A (en) * 1988-11-01 1989-08-22 The Board Of Trustees Of The University Of Illinois Continuous phase shifter for a phased array hyperthermia system
GB2248356A (en) * 1990-09-28 1992-04-01 Philips Electronic Associated Analogue-to-digital converter
GB9313020D0 (en) * 1993-06-24 1993-08-11 Madge Networks Ltd Jitter monitoring
US5479457A (en) * 1993-08-27 1995-12-26 Vlsi Technology Inc. Method and apparatus for attenuating jitter in a digital transmission line
US5856804A (en) * 1996-10-30 1999-01-05 Motorola, Inc. Method and intelligent digital beam forming system with improved signal quality communications
US6076175A (en) * 1997-03-31 2000-06-13 Sun Microsystems, Inc. Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
JP2002217258A (ja) * 2001-01-22 2002-08-02 Hitachi Ltd 半導体装置およびその測定方法、ならびに半導体装置の製造方法
US6625560B1 (en) * 2001-07-13 2003-09-23 Silicon Image, Inc. Method of testing serial interface
US6847247B2 (en) * 2001-11-27 2005-01-25 Sun Microsystems, Inc. Jittery polyphase clock
US6885209B2 (en) * 2002-08-21 2005-04-26 Intel Corporation Device testing
US7047457B1 (en) * 2003-09-11 2006-05-16 Xilinx, Inc. Testing of a multi-gigabit transceiver
JP2007514388A (ja) * 2003-12-16 2007-05-31 カリフォルニア インスティテュート オブ テクノロジー デターミニスティックジッターイコライザ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06152579A (ja) * 1992-11-05 1994-05-31 Fujikura Ltd ジッタ抑制回路
JPH11308282A (ja) * 1998-04-20 1999-11-05 Fuji Electric Co Ltd フィールドバス伝送信号のジッタ補正回路
JP2000183992A (ja) * 1998-12-18 2000-06-30 Toshiba Corp クロック再生方法および回路
JP2002340985A (ja) * 2001-05-21 2002-11-27 Hitachi Ltd 負荷電流出力回路一体形ドライバ回路及、それを備えたピンエレクトロニクスｉｃ及びｉｃテスタ

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Publication number Publication date
US7609758B2 (en) 2009-10-27
US20050243960A1 (en) 2005-11-03

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