JP2005159166A - Cmp用スラリー、研磨方法、および半導体装置の製造方法 - Google Patents
Cmp用スラリー、研磨方法、および半導体装置の製造方法 Download PDFInfo
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- JP2005159166A JP2005159166A JP2003398163A JP2003398163A JP2005159166A JP 2005159166 A JP2005159166 A JP 2005159166A JP 2003398163 A JP2003398163 A JP 2003398163A JP 2003398163 A JP2003398163 A JP 2003398163A JP 2005159166 A JP2005159166 A JP 2005159166A
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K3/00—Materials not provided for elsewhere
- C09K3/14—Anti-slip materials; Abrasives
- C09K3/1454—Abrasive powders, suspensions and pastes for polishing
- C09K3/1463—Aqueous liquid suspensions
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F3/00—Brightening metals by chemical means
- C23F3/04—Heavy metals
- C23F3/06—Heavy metals with acidic solutions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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Abstract
【解決手段】 Cuの酸化剤、Cu有機錯体を形成する錯体形成剤、界面活性剤、無機粒子、および、1重量%未満の濃度で配合され、ポリスチレンを含むとともに、前記無機粒子と同極性の官能基を表面に有する平均粒子径100nm未満の樹脂粒子を含有することを特徴とする。
【選択図】 なし
Description
Cu有機錯体を形成する錯体形成剤、
界面活性剤、
無機粒子、および
1重量%未満の濃度で配合され、ポリスチレンを含むとともに、前記無機粒子と同極性の官能基を表面に有する平均粒子径100nm未満の樹脂粒子を含有することを特徴とする。
前記研磨布上に、前述のCMP用スラリーを滴下して、前記被研磨面を研磨する工程を具備することを特徴とする。
前記絶縁膜に凹部を形成する工程と、
前記凹部の内部および前記絶縁膜の上に導電性材料を堆積して、導電性を有する層を形成する工程と、
前記絶縁膜の上に堆積された前記導電性材料を除去して、前記導電性材料を前記凹部内部に残置する工程とを具備し、
前記絶縁膜上に堆積された前記導電性材料の除去は、前述のスラリーを用いたCMPにより行なわれることを特徴とする。
以下の成分(a)〜(e)を溶媒としての純水に加えて、スラリーサンプル1を調製した。
錯体形成剤(b):キナルジン酸0.2重量%、キノリン酸:0.25重量%
アラニン:0.25重量%
ドデシルベンゼンスルホン酸カリウム:0.04重量%
界面活性剤(c):アセチレンジオール系ノニオン
(分子量1529、HLB値18):0.1重量%
無機粒子(d):コロイダルシリカ25nm:0.4重量%
樹脂粒子(e):架橋ポリスチレン製 0.5重量%
平均粒子径:50nm
表面官能基:COOH
ここで用いた樹脂粒子は、公知の方法により製造することができる。例えば、ジビニルベンゼン、メタクリル酸、ヒドロキシエチルアクリレート、ラウリル硫酸アンモニウム、および過硫酸アンモニウムを純水に溶解させ、窒素ガス雰囲気下、攪拌しながら70℃に昇温して、6時間重合させた。こうして、官能基としてのCOOH基を表面に有する架橋ポリスチレンからなる樹脂粒子が得られた。なお、重合収率は95%であり、電導度滴定法により測定したカルボキシル基の分布は、粒子内部が40%、粒子表面が50%、水相部が10%であった。TEM観察により樹脂粒子の平均粒子径を求めたところ、50nmであった。
無機粒子としては、フュームドアルミナとフュームドチタニアとを用意した。これらの無機粒子は、いずれも一次粒子径は20nmであり、二次粒子径は0.1μmである。また、平均粒子径30nmの架橋ポリスチレン製粒子の表面に、COOHまたはNH2を結合させて、2種類の樹脂粒子を用意した。こうした無機粒子と樹脂粒子とを組み合わせて用いる以外は、前述のNo.1のサンプルと同様の処方により4種類のサンプルを調製した。無機粒子および樹脂粒子の濃度は、いずれも0.5重量%とした。
以下の成分(a)〜(e)を溶媒としての純水に加えて、No.49のスラリーサンプルを調製した。
錯体形成剤(b):キノリン酸:0.25重量%
界面活性剤(c):ポリオキシエチレンアルキレンエーテル
(分子量3000、HLB値17):0.05重量%
無機粒子(d):コロイダルシリカ25nm:3重量%
樹脂粒子(e):架橋ポリスチレン製 0.8重量%
平均粒子径:30nm
表面官能基:COOH
pH調整剤としてのKOHを添加して、pHを10に調整した。pH10においては、無機粒子としてのシリカ、および樹脂粒子の表面官能基であるCOOHは、いずれも負に帯電している。
13…凹部,14…Ta膜,15…Cu膜,A…オーバープレーティング部
16…第1の保護膜,17…第2の保護膜,18…無機粒子,19…樹脂粒子
20…水の馴染まない領域,21…半導体基板,22…無機絶縁膜,23…Wプラグ
24…Ta膜,25…Cu膜,26…SiN膜,27…LKD5109膜
28…ブラックダイアモンド膜,29…無機SiO2膜
B…配線幅30μm領域,h1…Cu凸部高さ,d1…Cu凹部深さ
h1…CMP後Cu凸部高さ,d2…ディッシング量,e…エロージョン量
30…ターンテーブル,31…研磨布,32…半導体基板,33…トップリング
34…水供給ノズル,35…スラリー供給ノズル,36…ドレッサー
37…スラリー,41…LKD5109膜,42…ブラックダイアモンド膜。
Claims (6)
- Cuの酸化剤、
Cu有機錯体を形成する錯体形成剤、
界面活性剤、
無機粒子、および
1重量%未満の濃度で配合され、ポリスチレンを含むとともに、前記無機粒子と同極性の官能基を表面に有する平均粒子径100nm未満の樹脂粒子を含有することを特徴とするCMP用スラリー。 - 前記樹脂粒子の平均粒子径は、20nm以上50nm以下であることを特徴とする請求項1に記載のCMP用スラリー。
- 前記樹脂粒子の濃度は、0.05重量%以上0.95重量%以下であることを特徴とする請求項1または2に記載のCMP用スラリー。
- 前記官能基は、カルボキシル基、スルホニル基、およびアミノ基からなる群から選択される少なくとも一種であることを特徴とする請求項1ないし3のいずれか1項に記載のCMP用スラリー。
- ターンテーブル上に貼付された研磨布に、被研磨面を有する半導体基板を当接させる工程、および
前記研磨布上に、請求項1ないし4のいずれか1項に記載のCMP用スラリーを滴下して、前記被研磨面を研磨する工程を具備することを特徴とする研磨方法。 - 半導体基板上に絶縁膜を形成する工程と、
前記絶縁膜に凹部を形成する工程と、
前記凹部の内部および前記絶縁膜の上に導電性材料を堆積して、導電性を有する層を形成する工程と、
前記絶縁膜の上に堆積された前記導電性材料を除去して、前記導電性材料を前記凹部内部に残置する工程とを具備し、
前記絶縁膜上に堆積された前記導電性材料の除去は、請求項1ないし4のいずれか1項に記載のスラリーを用いたCMPにより行なわれることを特徴とする半導体装置の製造方法。
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US10/932,096 US7419910B2 (en) | 2003-11-27 | 2004-09-02 | Slurry for CMP, polishing method and method of manufacturing semiconductor device |
TW093135901A TWI277647B (en) | 2003-11-27 | 2004-11-22 | Slurry for CMP, polishing method and method of manufacturing semiconductor device |
CN200410096136.3A CN1626600A (zh) | 2003-11-27 | 2004-11-26 | Cmp浆料、抛光方法和半导体器件的制造方法 |
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