JP2005101144A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】この半導体装置50は、回路を含む半導体チップ5の上面に接触するように形成された単一の材料(SiO2)からなる絶縁膜6と、絶縁膜6の上面に接触するように形成されたエクステンションパッド13と、半導体チップ5の側面から下面に沿って延びるように形成され、絶縁膜6の一部を除去することにより露出されたエクステンションパッド13の下面に対して接続された配線16とを備えている。
【選択図】図2
Description
図1は、本発明の第1実施形態による半導体装置の全体構成を示した側面図である。図2は、図1に示した第1実施形態による半導体装置の端部近傍における構造を示した断面図である。まず、図1および図2を参照して、本発明の第1実施形態による半導体装置の構造について説明する。
図19は、本発明の第2実施形態による半導体装置の端部近傍の構造を示した断面図である。この第2実施形態では、上記第1実施形態と異なり、エクステンションパッドの幅が絶縁膜の開口部の大きさよりも小さくなるように形成された例について説明する。まず、図19を参照して、本発明の第2実施形態による半導体装置の構造について説明する。なお、第1実施形態と同一の要素には、同一の符号を付している。
6 絶縁膜(第1絶縁膜)
10、30 絶縁膜(第2絶縁膜)
11、31 開口部(第1開口部)
12、32 コンタクトホール(第2開口部)
13、33 エクステンションパッド(第1配線)
14、34 配線(第3配線)
16 配線(第2配線)
17 絶縁膜(第3絶縁膜)
Claims (8)
- 回路を含む半導体チップの上面に接触するように形成された単一の材料からなる第1絶縁膜と、
前記第1絶縁膜の上面に接触するように形成された第1配線と、
前記半導体チップの側面から下面に沿って延びるように形成され、前記第1絶縁膜の一部を除去することにより露出された第1配線の下面に対して接続された第2配線とを備えた、半導体装置。 - 前記第1絶縁膜上に形成され、前記第1絶縁膜とは異なる材料からなるとともに、第1開口部を有する第2絶縁膜をさらに備え、
前記第1配線の下面は、前記第2絶縁膜の第1開口部を介して前記第1絶縁膜の上面および前記第2配線に接触している、請求項1に記載の半導体装置。 - 前記第2絶縁膜上に形成された第3配線をさらに備え、
前記第2絶縁膜は、前記第3配線と前記半導体チップの回路とを接続するための第2開口部を含む、請求項2に記載の半導体装置。 - 前記半導体チップと前記第2配線との間に、前記半導体チップと前記第2配線とを絶縁するように設けられるとともに、前記第1絶縁膜の下面の所定の領域を覆うように形成された前記第1絶縁膜と実質的に同一のエッチング手段により除去することが可能な材料からなる第3絶縁膜をさらに備えた、請求項1〜3のいずれか1項に記載の半導体装置。
- 回路を含む半導体チップの上面に接触するように、単一の材料からなる第1絶縁膜を形成する工程と、
前記第1絶縁膜の上面に下面が接触するように第1配線を形成する工程と、
少なくとも前記第1絶縁膜の一部を下面側からエッチングすることによって、前記第1配線の下面を露出させる工程と、
露出された前記第1配線の下面に対して第2配線を接続する工程とを備えた、半導体装置の製造方法。 - 前記第1絶縁膜の上面に下面が接触するように第1配線を形成する工程に先立って、
前記第1絶縁膜上に第2絶縁膜を形成する工程と、
前記第2絶縁膜に第1開口部を形成する工程とをさらに備え、
前記第1絶縁膜の上面に下面が接触するように第1配線を形成する工程は、前記第2絶縁膜の第1開口部を介して、前記第1絶縁膜の上面に下面が接触するように前記第1配線を形成する工程を含む、請求項5に記載の半導体装置の製造方法。 - 前記第2絶縁膜上に第3配線を形成する工程をさらに備え、
前記第2絶縁膜に第1開口部を形成する工程は、
前記第2絶縁膜をエッチングすることにより、前記第2絶縁膜に、前記第1開口部と、前記第3配線および前記半導体チップの回路を接続するための第2開口部とを実質的に同時に形成する工程を含む、請求項6に記載の半導体装置の製造方法。 - 前記第1配線の下面を露出させる工程に先立って、前記第1絶縁膜の下面を覆うように前記第1絶縁膜と実質的に同一のエッチング手段により除去することが可能な材料からなる第3絶縁膜を形成する工程をさらに備え、
前記第1配線の下面を露出させる工程は、
前記第3絶縁膜および前記第1絶縁膜の一部を下側から前記同一のエッチング手段により連続的にエッチングすることによって、前記第1配線の下面を露出させる工程を含む、請求項5〜7のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003331142A JP4248355B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体装置および半導体装置の製造方法 |
TW093128145A TWI323001B (en) | 2003-09-24 | 2004-09-17 | Semiconductor device and method of fabricating semiconductor device |
CNB2004100825617A CN100466248C (zh) | 2003-09-24 | 2004-09-20 | 半导体装置及半导体装置的制造方法 |
US10/945,945 US7112881B2 (en) | 2003-09-24 | 2004-09-22 | Semiconductor device |
KR1020040076411A KR100616051B1 (ko) | 2003-09-24 | 2004-09-23 | 반도체 장치 및 반도체 장치의 제조 방법 |
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JP2003331142A JP4248355B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体装置および半導体装置の製造方法 |
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JP2005101144A true JP2005101144A (ja) | 2005-04-14 |
JP4248355B2 JP4248355B2 (ja) | 2009-04-02 |
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US (1) | US7112881B2 (ja) |
JP (1) | JP4248355B2 (ja) |
KR (1) | KR100616051B1 (ja) |
CN (1) | CN100466248C (ja) |
TW (1) | TWI323001B (ja) |
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TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
JP4401181B2 (ja) * | 2003-08-06 | 2010-01-20 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP4322181B2 (ja) * | 2004-07-29 | 2009-08-26 | 三洋電機株式会社 | 半導体装置の製造方法 |
TWI324800B (en) * | 2005-12-28 | 2010-05-11 | Sanyo Electric Co | Method for manufacturing semiconductor device |
TW200737506A (en) * | 2006-03-07 | 2007-10-01 | Sanyo Electric Co | Semiconductor device and manufacturing method of the same |
JP5258567B2 (ja) * | 2006-08-11 | 2013-08-07 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置及びその製造方法 |
JP5010247B2 (ja) * | 2006-11-20 | 2012-08-29 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP5101157B2 (ja) * | 2007-05-07 | 2012-12-19 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法 |
TWI492358B (zh) * | 2012-09-26 | 2015-07-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
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IL108359A (en) * | 1994-01-17 | 2001-04-30 | Shellcase Ltd | Method and device for creating integrated circular devices |
US6124179A (en) * | 1996-09-05 | 2000-09-26 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
US5677562A (en) * | 1996-05-14 | 1997-10-14 | General Instrument Corporation Of Delaware | Planar P-N junction semiconductor structure with multilayer passivation |
IL123207A0 (en) | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
WO1999048143A2 (en) * | 1998-03-16 | 1999-09-23 | Koninklijke Philips Electronics N.V. | Method of manufacturing semiconductor devices with 'chip size package' |
JP2001077229A (ja) * | 1999-09-02 | 2001-03-23 | Matsushita Electronics Industry Corp | 半導体装置およびその製造方法 |
JP2002359347A (ja) * | 2001-03-28 | 2002-12-13 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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- 2004-09-20 CN CNB2004100825617A patent/CN100466248C/zh not_active Expired - Fee Related
- 2004-09-22 US US10/945,945 patent/US7112881B2/en active Active
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JP4248355B2 (ja) | 2009-04-02 |
US7112881B2 (en) | 2006-09-26 |
CN1601743A (zh) | 2005-03-30 |
CN100466248C (zh) | 2009-03-04 |
TWI323001B (en) | 2010-04-01 |
KR100616051B1 (ko) | 2006-08-28 |
US20050062146A1 (en) | 2005-03-24 |
KR20050030148A (ko) | 2005-03-29 |
TW200512797A (en) | 2005-04-01 |
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