JP2005071556A - 半導体記憶装置および半導体集積回路装置 - Google Patents

半導体記憶装置および半導体集積回路装置 Download PDF

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Publication number
JP2005071556A
JP2005071556A JP2003304013A JP2003304013A JP2005071556A JP 2005071556 A JP2005071556 A JP 2005071556A JP 2003304013 A JP2003304013 A JP 2003304013A JP 2003304013 A JP2003304013 A JP 2003304013A JP 2005071556 A JP2005071556 A JP 2005071556A
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JP
Japan
Prior art keywords
circuit
power supply
memory
switch
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003304013A
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English (en)
Japanese (ja)
Other versions
JP2005071556A5 (https=
Inventor
Noriyoshi Watabe
憲佳 渡部
Noriaki Maeda
徳章 前田
Masanao Yamaoka
雅直 山岡
Yoshihiro Shinozaki
義弘 篠崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
SuperH Inc
Renesas Semiconductor Package and Test Solutions Co Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Renesas Technology Corp
Hitachi ULSI Systems Co Ltd
Renesas Northern Japan Semiconductor Inc
SuperH Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Hitachi ULSI Systems Co Ltd, Renesas Northern Japan Semiconductor Inc, SuperH Inc filed Critical Renesas Technology Corp
Priority to JP2003304013A priority Critical patent/JP2005071556A/ja
Priority to US10/927,052 priority patent/US7031220B2/en
Publication of JP2005071556A publication Critical patent/JP2005071556A/ja
Priority to US11/353,967 priority patent/US7251182B2/en
Publication of JP2005071556A5 publication Critical patent/JP2005071556A5/ja
Priority to US11/812,596 priority patent/US7385870B2/en
Priority to US12/117,804 priority patent/US20080247258A1/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP2003304013A 2003-08-28 2003-08-28 半導体記憶装置および半導体集積回路装置 Pending JP2005071556A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003304013A JP2005071556A (ja) 2003-08-28 2003-08-28 半導体記憶装置および半導体集積回路装置
US10/927,052 US7031220B2 (en) 2003-08-28 2004-08-27 Semiconductor memory device and semiconductor integrated circuit device
US11/353,967 US7251182B2 (en) 2003-08-28 2006-02-15 Semiconductor memory device and semiconductor integrated circuit device
US11/812,596 US7385870B2 (en) 2003-08-28 2007-06-20 Semiconductor memory device and semiconductor integrated circuit device
US12/117,804 US20080247258A1 (en) 2003-08-28 2008-05-09 Semiconductor memory device and semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003304013A JP2005071556A (ja) 2003-08-28 2003-08-28 半導体記憶装置および半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2005071556A true JP2005071556A (ja) 2005-03-17
JP2005071556A5 JP2005071556A5 (https=) 2006-10-05

Family

ID=34225077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003304013A Pending JP2005071556A (ja) 2003-08-28 2003-08-28 半導体記憶装置および半導体集積回路装置

Country Status (2)

Country Link
US (4) US7031220B2 (https=)
JP (1) JP2005071556A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7869299B2 (en) 2007-10-29 2011-01-11 Elpida Memory, Inc. Internal-voltage generating circuit and semiconductor device including the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP2004021574A (ja) * 2002-06-17 2004-01-22 Hitachi Ltd 半導体装置
JP2005071556A (ja) * 2003-08-28 2005-03-17 Renesas Technology Corp 半導体記憶装置および半導体集積回路装置
JP4549711B2 (ja) * 2004-03-29 2010-09-22 ルネサスエレクトロニクス株式会社 半導体回路装置
US20100138451A1 (en) * 2006-04-03 2010-06-03 Assaf Henkin Techniques for facilitating on-line contextual analysis and advertising
US7400546B1 (en) 2007-11-15 2008-07-15 International Business Machines Corporation Low overhead switched header power savings apparatus
US7791977B2 (en) * 2007-11-15 2010-09-07 International Business Machines Corporation Design structure for low overhead switched header power savings apparatus
US7848172B2 (en) * 2008-11-24 2010-12-07 Agere Systems Inc. Memory circuit having reduced power consumption
JP2011123970A (ja) 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
US20130128684A1 (en) * 2011-05-09 2013-05-23 International Business Machines Corporation Reduced leakage banked wordline header
US8675420B2 (en) * 2011-05-26 2014-03-18 Micron Technology, Inc. Devices and systems including enabling circuits
JP2013191262A (ja) * 2012-03-15 2013-09-26 Elpida Memory Inc 半導体装置
US9671855B2 (en) * 2014-06-30 2017-06-06 Micron Technology, Inc. Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation
US10186313B2 (en) 2016-04-28 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Memory macro disableable input-output circuits and methods of operating the same

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US4151611A (en) * 1976-03-26 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Power supply control system for memory systems
JPS5927349A (ja) * 1982-08-03 1984-02-13 Sharp Corp 電子機器
EP0288687B1 (en) * 1987-03-03 1994-12-28 Takeda Chemical Industries, Ltd. Monoclonal antibody, hybridoma, their production and use thereof
JP2735435B2 (ja) * 1992-06-01 1998-04-02 三菱電機株式会社 メモリカードのメモリ制御用回路
JPH09106329A (ja) * 1995-10-12 1997-04-22 Mitsubishi Electric Corp メモリカード
US5774405A (en) * 1996-03-28 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory having an internal circuit using a boosted potential
JPH1049391A (ja) * 1996-08-05 1998-02-20 Nec Corp プログラム受信機能付エージェント装置
US5901103A (en) * 1997-04-07 1999-05-04 Motorola, Inc. Integrated circuit having standby control for memory and method thereof
JP4074697B2 (ja) * 1997-11-28 2008-04-09 株式会社ルネサステクノロジ 半導体装置
JP3741534B2 (ja) * 1998-03-24 2006-02-01 株式会社リコー 半導体メモリ
WO1999067791A1 (de) * 1998-06-24 1999-12-29 Infineon Technologies Ag Elektronische prüfungsspeichereinrichtung
JP2001052476A (ja) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp 半導体装置
JP2001118399A (ja) * 1999-10-20 2001-04-27 Mitsubishi Electric Corp 半導体集積回路装置
JP3998908B2 (ja) * 2000-10-23 2007-10-31 松下電器産業株式会社 不揮発性メモリ装置
JP4817510B2 (ja) * 2001-02-23 2011-11-16 キヤノン株式会社 メモリコントローラ及びメモリ制御装置
KR100456597B1 (ko) * 2002-07-16 2004-11-09 삼성전자주식회사 외부 전압 레벨에 따라 내부 전압을 선택적으로 발생하는반도체 메모리 장치 및 그 내부 전압 발생 회로
JP2005071556A (ja) * 2003-08-28 2005-03-17 Renesas Technology Corp 半導体記憶装置および半導体集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7869299B2 (en) 2007-10-29 2011-01-11 Elpida Memory, Inc. Internal-voltage generating circuit and semiconductor device including the same

Also Published As

Publication number Publication date
US20060133180A1 (en) 2006-06-22
US7251182B2 (en) 2007-07-31
US7385870B2 (en) 2008-06-10
US7031220B2 (en) 2006-04-18
US20080247258A1 (en) 2008-10-09
US20070247952A1 (en) 2007-10-25
US20050052925A1 (en) 2005-03-10

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