JP2004531830A5 - - Google Patents

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Publication number
JP2004531830A5
JP2004531830A5 JP2003507709A JP2003507709A JP2004531830A5 JP 2004531830 A5 JP2004531830 A5 JP 2004531830A5 JP 2003507709 A JP2003507709 A JP 2003507709A JP 2003507709 A JP2003507709 A JP 2003507709A JP 2004531830 A5 JP2004531830 A5 JP 2004531830A5
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JP
Japan
Prior art keywords
communication bus
bus
control
burst
masters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003507709A
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English (en)
Japanese (ja)
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JP2004531830A (ja
JP4139771B2 (ja
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Publication date
Priority claimed from US09/888,278 external-priority patent/US6775727B2/en
Application filed filed Critical
Publication of JP2004531830A publication Critical patent/JP2004531830A/ja
Publication of JP2004531830A5 publication Critical patent/JP2004531830A5/ja
Application granted granted Critical
Publication of JP4139771B2 publication Critical patent/JP4139771B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2003507709A 2001-06-23 2002-05-15 キャッシュメモリバーストサイクル中にバスアービトレーションを制御するためのシステム及び方法 Expired - Lifetime JP4139771B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/888,278 US6775727B2 (en) 2001-06-23 2001-06-23 System and method for controlling bus arbitration during cache memory burst cycles
PCT/US2002/018358 WO2003001388A1 (en) 2001-06-23 2002-05-15 System and method for controlling bus arbitration during cache memory burst cycles

Publications (3)

Publication Number Publication Date
JP2004531830A JP2004531830A (ja) 2004-10-14
JP2004531830A5 true JP2004531830A5 (enExample) 2005-12-22
JP4139771B2 JP4139771B2 (ja) 2008-08-27

Family

ID=25392904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003507709A Expired - Lifetime JP4139771B2 (ja) 2001-06-23 2002-05-15 キャッシュメモリバーストサイクル中にバスアービトレーションを制御するためのシステム及び方法

Country Status (8)

Country Link
US (1) US6775727B2 (enExample)
JP (1) JP4139771B2 (enExample)
KR (1) KR100899951B1 (enExample)
CN (1) CN1230758C (enExample)
DE (1) DE10296959T5 (enExample)
GB (1) GB2390200B (enExample)
TW (1) TWI221968B (enExample)
WO (1) WO2003001388A1 (enExample)

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US8001538B2 (en) 2005-12-07 2011-08-16 Microsoft Corporation Software accessible cache metadata
US8225297B2 (en) 2005-12-07 2012-07-17 Microsoft Corporation Cache metadata identifiers for isolation and sharing
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US8478920B2 (en) * 2010-06-24 2013-07-02 International Business Machines Corporation Controlling data stream interruptions on a shared interface
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)
CN102724389B (zh) * 2011-11-15 2017-06-13 新奥特（北京）视频技术有限公司 一种同平台非编系统间的监视器输出方法
FR2982961B1 (fr) * 2011-11-22 2014-09-05 Schneider Electric Usa Inc Arbitrage de dispositif de commande prioritaire
TWI506536B (zh) 2013-01-10 2015-11-01 Accton Technology Corp 執行裝置及其堆疊方法與堆疊系統
CN103257942B (zh) * 2013-03-27 2015-12-02 青岛中星微电子有限公司 一种片上系统共享总线请求处理的方法及装置
US9606853B2 (en) * 2014-03-28 2017-03-28 Intel Corporation Protecting a memory device from becoming unusable
US10289596B2 (en) 2016-06-07 2019-05-14 Macronix International Co., Ltd. Memory and method for operating a memory with interruptible command sequence
US10475492B1 (en) 2018-07-27 2019-11-12 Macronix International Co., Ltd. Circuit and method for read latency control

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