JP2004362756A5 - - Google Patents

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Publication number
JP2004362756A5
JP2004362756A5 JP2004161460A JP2004161460A JP2004362756A5 JP 2004362756 A5 JP2004362756 A5 JP 2004362756A5 JP 2004161460 A JP2004161460 A JP 2004161460A JP 2004161460 A JP2004161460 A JP 2004161460A JP 2004362756 A5 JP2004362756 A5 JP 2004362756A5
Authority
JP
Japan
Prior art keywords
data
integrated circuit
circuit device
write
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004161460A
Other languages
English (en)
Japanese (ja)
Other versions
JP4819325B2 (ja
JP2004362756A (ja
Filing date
Publication date
Priority claimed from KR10-2003-0042840A external-priority patent/KR100532444B1/ko
Priority claimed from US10/792,425 external-priority patent/US7054202B2/en
Application filed filed Critical
Publication of JP2004362756A publication Critical patent/JP2004362756A/ja
Publication of JP2004362756A5 publication Critical patent/JP2004362756A5/ja
Application granted granted Critical
Publication of JP4819325B2 publication Critical patent/JP4819325B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2004161460A 2003-06-03 2004-05-31 集積回路装置及びその動作方法 Expired - Fee Related JP4819325B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR20030035604 2003-06-03
KR2003-035604 2003-06-03
KR10-2003-0042840A KR100532444B1 (ko) 2003-06-03 2003-06-27 Ｎ 비트 프리패치 구조로 2ｎ 비트 프리패치 스킴을구현하는 메모리 장치 및 이 메모리 장치의 2ｎ 비트프리패치 방법 및 자동 프리차아지 방법
KR2003-042840 2003-06-27
US10/792425 2004-03-03
US10/792,425 US7054202B2 (en) 2003-06-03 2004-03-03 High burst rate write data paths for integrated circuit memory devices and methods of operating same

Publications (3)

Publication Number Publication Date
JP2004362756A JP2004362756A (ja) 2004-12-24
JP2004362756A5 true JP2004362756A5 (zh) 2007-03-22
JP4819325B2 JP4819325B2 (ja) 2011-11-24

Family

ID=33545117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004161460A Expired - Fee Related JP4819325B2 (ja) 2003-06-03 2004-05-31 集積回路装置及びその動作方法

Country Status (4)

Country Link
JP (1) JP4819325B2 (zh)
DE (1) DE102004026526B4 (zh)
GB (1) GB2403575B (zh)
TW (1) TWI250530B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005001894A1 (de) 2005-01-14 2006-08-03 Infineon Technologies Ag Synchroner Parallel-Serienwandler
JP5052056B2 (ja) * 2005-09-29 2012-10-17 エスケーハイニックス株式会社 半導体メモリ素子のデータ入力装置
JP4470183B2 (ja) 2006-08-28 2010-06-02 エルピーダメモリ株式会社 半導体記憶装置
KR20080065100A (ko) 2007-01-08 2008-07-11 주식회사 하이닉스반도체 반도체 메모리 소자와 그의 구동 방법
KR101094946B1 (ko) 2010-01-29 2011-12-15 주식회사 하이닉스반도체 반도체 집적 회로
JP2013206492A (ja) 2012-03-27 2013-10-07 Toshiba Corp 半導体装置およびその駆動方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180871A (ja) * 1983-03-31 1984-10-15 Fujitsu Ltd 半導体メモリ装置
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing
JPH0740430B2 (ja) * 1986-07-04 1995-05-01 日本電気株式会社 メモリ装置
TW293107B (zh) * 1994-10-28 1996-12-11 Matsushita Electric Ind Co Ltd
JP3788867B2 (ja) * 1997-10-28 2006-06-21 株式会社東芝 半導体記憶装置
US6459393B1 (en) * 1998-05-08 2002-10-01 International Business Machines Corporation Apparatus and method for optimized self-synchronizing serializer/deserializer/framer
JP2000163969A (ja) * 1998-09-16 2000-06-16 Fujitsu Ltd 半導体記憶装置
DE19951677B4 (de) * 1998-10-30 2006-04-13 Fujitsu Ltd., Kawasaki Halbleiterspeichervorrichtung
JP3859885B2 (ja) * 1998-11-24 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
JP4083944B2 (ja) * 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置

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