JP2004135318A5 - - Google Patents

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Publication number
JP2004135318A5
JP2004135318A5 JP2003323294A JP2003323294A JP2004135318A5 JP 2004135318 A5 JP2004135318 A5 JP 2004135318A5 JP 2003323294 A JP2003323294 A JP 2003323294A JP 2003323294 A JP2003323294 A JP 2003323294A JP 2004135318 A5 JP2004135318 A5 JP 2004135318A5
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JP
Japan
Prior art keywords
input
gate
signal
retiming
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003323294A
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English (en)
Japanese (ja)
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JP2004135318A (ja
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Publication date
Priority claimed from US10/268,196 external-priority patent/US6686777B1/en
Application filed filed Critical
Publication of JP2004135318A publication Critical patent/JP2004135318A/ja
Publication of JP2004135318A5 publication Critical patent/JP2004135318A5/ja
Withdrawn legal-status Critical Current

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JP2003323294A 2002-10-09 2003-09-16 改善されたタイミングマージンを有する位相検出器 Withdrawn JP2004135318A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/268,196 US6686777B1 (en) 2002-10-09 2002-10-09 Phase detector having improved timing margins

Publications (2)

Publication Number Publication Date
JP2004135318A JP2004135318A (ja) 2004-04-30
JP2004135318A5 true JP2004135318A5 (enExample) 2007-01-25

Family

ID=30443855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003323294A Withdrawn JP2004135318A (ja) 2002-10-09 2003-09-16 改善されたタイミングマージンを有する位相検出器

Country Status (5)

Country Link
US (1) US6686777B1 (enExample)
EP (1) EP1408643B1 (enExample)
JP (1) JP2004135318A (enExample)
CN (1) CN100504403C (enExample)
DE (1) DE60318162T2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7505541B1 (en) * 2003-01-17 2009-03-17 Xilinx, Inc. NRZ/PAM-4/PRML triple mode phase and data detector
US6956923B1 (en) * 2003-01-17 2005-10-18 Xilinx, Inc. High speed phase detector architecture
US7805083B2 (en) * 2003-04-28 2010-09-28 Alcatel-Lucent Usa Inc. Method and apparatus for data recovery in an optical transmission system
US7057435B2 (en) * 2003-05-30 2006-06-06 Regents Of The University Of California Distributed delay-locked-based clock and data recovery systems
KR100479309B1 (ko) * 2003-07-26 2005-03-28 삼성전자주식회사 위상차 검출 방법 및 이를 수행하기 위한 위상 검출기
US7049869B2 (en) * 2003-09-02 2006-05-23 Gennum Corporation Adaptive lock position circuit
CN1937605B (zh) * 2005-09-19 2010-12-01 中兴通讯股份有限公司 一种相位获取装置
US7873132B2 (en) * 2005-09-21 2011-01-18 Hewlett-Packard Development Company, L.P. Clock recovery
KR100656464B1 (ko) * 2005-12-28 2006-12-11 주식회사 하이닉스반도체 반도체 메모리의 출력 인에이블 신호 생성장치 및 방법
US20080056403A1 (en) * 2006-09-01 2008-03-06 On Demand Microelectronics Method and apparatus for timing recovery of pam signals
US8019022B2 (en) * 2007-03-22 2011-09-13 Mediatek Inc. Jitter-tolerance-enhanced CDR using a GDCO-based phase detector
JP5148398B2 (ja) * 2008-07-23 2013-02-20 アンリツ株式会社 デマルチプレクサ
TWI555338B (zh) * 2014-11-14 2016-10-21 円星科技股份有限公司 相位偵測器及相關的相位偵測方法
WO2019049524A1 (ja) * 2017-09-11 2019-03-14 ソニーセミコンダクタソリューションズ株式会社 データ受信装置及びデータ送受信装置
US11283436B2 (en) * 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719508A (en) * 1996-02-01 1998-02-17 Northern Telecom, Ltd. Loss of lock detector for master timing generator
CA2201695C (en) * 1997-04-03 2004-08-10 Gennum Corporation Phase detector for high speed clock recovery from random binary signals
US6483871B1 (en) * 1998-12-28 2002-11-19 Nortel Networks Limited Phase detector with adjustable set point

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