JP2004117344A5 - - Google Patents

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Publication number
JP2004117344A5
JP2004117344A5 JP2003311323A JP2003311323A JP2004117344A5 JP 2004117344 A5 JP2004117344 A5 JP 2004117344A5 JP 2003311323 A JP2003311323 A JP 2003311323A JP 2003311323 A JP2003311323 A JP 2003311323A JP 2004117344 A5 JP2004117344 A5 JP 2004117344A5
Authority
JP
Japan
Prior art keywords
signal
bit stream
transition
bitstream
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2003311323A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004117344A (ja
Filing date
Publication date
Priority claimed from EP02021145A external-priority patent/EP1316808B1/en
Application filed filed Critical
Publication of JP2004117344A publication Critical patent/JP2004117344A/ja
Publication of JP2004117344A5 publication Critical patent/JP2004117344A5/ja
Ceased legal-status Critical Current

Links

JP2003311323A 2002-09-24 2003-09-03 ビットストリームの遷移を調節する方法 Ceased JP2004117344A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02021145A EP1316808B1 (en) 2002-09-24 2002-09-24 Transition adjustment

Publications (2)

Publication Number Publication Date
JP2004117344A JP2004117344A (ja) 2004-04-15
JP2004117344A5 true JP2004117344A5 (enExample) 2007-02-22

Family

ID=8185482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003311323A Ceased JP2004117344A (ja) 2002-09-24 2003-09-03 ビットストリームの遷移を調節する方法

Country Status (5)

Country Link
US (1) US9103887B2 (enExample)
EP (1) EP1316808B1 (enExample)
JP (1) JP2004117344A (enExample)
CN (1) CN1318853C (enExample)
DE (1) DE60200289T2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7526054B2 (en) * 2005-03-04 2009-04-28 Analog Devices, Inc. Method, article, and apparatus for a dynamic phase delay compensator
US7394277B2 (en) * 2006-04-20 2008-07-01 Advantest Corporation Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method
US20090113245A1 (en) * 2007-10-30 2009-04-30 Teradyne, Inc. Protocol aware digital channel apparatus
KR102458563B1 (ko) * 2018-02-12 2022-10-28 한국전자통신연구원 백스캐터 통신을 사용한 통신 방법 및 통신 장치
CN112104339B (zh) * 2020-08-28 2021-06-01 电子科技大学 一种适用于含跳变边沿信号的平滑滤波方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07123218B2 (ja) 1986-05-16 1995-12-25 株式会社トプコン 走査同期信号発生回路
JPS6331212A (ja) 1986-07-24 1988-02-09 Nec Corp 位相同期回路
US4814879A (en) 1987-08-07 1989-03-21 Rca Licensing Corporation Signal phase alignment circuitry
JP2527017B2 (ja) 1988-11-22 1996-08-21 ヤマハ株式会社 デジタルフィルタ
US5272729A (en) * 1991-09-20 1993-12-21 International Business Machines Corporation Clock signal latency elimination network
US5436937A (en) * 1993-02-01 1995-07-25 Motorola, Inc. Multi-mode digital phase lock loop
JP3636506B2 (ja) * 1995-06-19 2005-04-06 株式会社アドバンテスト 半導体試験装置
JP3502450B2 (ja) * 1994-08-22 2004-03-02 株式会社アドバンテスト パターン発生器
TW422927B (en) * 1998-02-09 2001-02-21 Advantest Corp Test apparatus for semiconductor device
US6100733A (en) * 1998-06-09 2000-08-08 Siemens Aktiengesellschaft Clock latency compensation circuit for DDR timing
US6820234B2 (en) * 1998-06-29 2004-11-16 Acuid Limited Skew calibration means and a method of skew calibration
US6181616B1 (en) * 1998-09-03 2001-01-30 Micron Technology, Inc. Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test
JP3114934B2 (ja) * 1998-10-09 2000-12-04 株式会社アドバンテスト 自動パターン同期回路及び同期方法
US6442223B1 (en) * 1999-04-26 2002-08-27 International Business Machines Corporation Method and system for data transfer
US6993695B2 (en) * 2001-06-06 2006-01-31 Agilent Technologies, Inc. Method and apparatus for testing digital devices using transition timestamps

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