CN1318853C - 跳变调整 - Google Patents

跳变调整 Download PDF

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Publication number
CN1318853C
CN1318853C CNB031495958A CN03149595A CN1318853C CN 1318853 C CN1318853 C CN 1318853C CN B031495958 A CNB031495958 A CN B031495958A CN 03149595 A CN03149595 A CN 03149595A CN 1318853 C CN1318853 C CN 1318853C
Authority
CN
China
Prior art keywords
bit stream
signal
bit
evaluated
saltus step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031495958A
Other languages
English (en)
Chinese (zh)
Other versions
CN1485624A (zh
Inventor
里瓦尔·约亨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of CN1485624A publication Critical patent/CN1485624A/zh
Application granted granted Critical
Publication of CN1318853C publication Critical patent/CN1318853C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CNB031495958A 2002-09-24 2003-07-17 跳变调整 Expired - Fee Related CN1318853C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02021145.4 2002-09-24
EP020211454 2002-09-24
EP02021145A EP1316808B1 (en) 2002-09-24 2002-09-24 Transition adjustment

Publications (2)

Publication Number Publication Date
CN1485624A CN1485624A (zh) 2004-03-31
CN1318853C true CN1318853C (zh) 2007-05-30

Family

ID=8185482

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031495958A Expired - Fee Related CN1318853C (zh) 2002-09-24 2003-07-17 跳变调整

Country Status (5)

Country Link
US (1) US9103887B2 (enExample)
EP (1) EP1316808B1 (enExample)
JP (1) JP2004117344A (enExample)
CN (1) CN1318853C (enExample)
DE (1) DE60200289T2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7526054B2 (en) * 2005-03-04 2009-04-28 Analog Devices, Inc. Method, article, and apparatus for a dynamic phase delay compensator
US7394277B2 (en) * 2006-04-20 2008-07-01 Advantest Corporation Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method
US20090113245A1 (en) * 2007-10-30 2009-04-30 Teradyne, Inc. Protocol aware digital channel apparatus
KR102458563B1 (ko) * 2018-02-12 2022-10-28 한국전자통신연구원 백스캐터 통신을 사용한 통신 방법 및 통신 장치
CN112104339B (zh) * 2020-08-28 2021-06-01 电子科技大学 一种适用于含跳变边沿信号的平滑滤波方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269410A (ja) * 1986-05-16 1987-11-21 Tokyo Optical Co Ltd 走査同期信号発生回路
JPS6331212A (ja) * 1986-07-24 1988-02-09 Nec Corp 位相同期回路
JPS6467029A (en) * 1987-08-07 1989-03-13 Rca Licensing Corp Phase matching circuit
JPH02141117A (ja) * 1988-11-22 1990-05-30 Yamaha Corp デジタルフィルタ

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272729A (en) * 1991-09-20 1993-12-21 International Business Machines Corporation Clock signal latency elimination network
US5436937A (en) * 1993-02-01 1995-07-25 Motorola, Inc. Multi-mode digital phase lock loop
JP3636506B2 (ja) * 1995-06-19 2005-04-06 株式会社アドバンテスト 半導体試験装置
JP3502450B2 (ja) * 1994-08-22 2004-03-02 株式会社アドバンテスト パターン発生器
TW422927B (en) * 1998-02-09 2001-02-21 Advantest Corp Test apparatus for semiconductor device
US6100733A (en) * 1998-06-09 2000-08-08 Siemens Aktiengesellschaft Clock latency compensation circuit for DDR timing
US6820234B2 (en) * 1998-06-29 2004-11-16 Acuid Limited Skew calibration means and a method of skew calibration
US6181616B1 (en) * 1998-09-03 2001-01-30 Micron Technology, Inc. Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test
JP3114934B2 (ja) * 1998-10-09 2000-12-04 株式会社アドバンテスト 自動パターン同期回路及び同期方法
US6442223B1 (en) * 1999-04-26 2002-08-27 International Business Machines Corporation Method and system for data transfer
US6993695B2 (en) * 2001-06-06 2006-01-31 Agilent Technologies, Inc. Method and apparatus for testing digital devices using transition timestamps

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269410A (ja) * 1986-05-16 1987-11-21 Tokyo Optical Co Ltd 走査同期信号発生回路
JPS6331212A (ja) * 1986-07-24 1988-02-09 Nec Corp 位相同期回路
JPS6467029A (en) * 1987-08-07 1989-03-13 Rca Licensing Corp Phase matching circuit
JPH02141117A (ja) * 1988-11-22 1990-05-30 Yamaha Corp デジタルフィルタ

Also Published As

Publication number Publication date
EP1316808B1 (en) 2004-03-24
JP2004117344A (ja) 2004-04-15
US20040057541A1 (en) 2004-03-25
US9103887B2 (en) 2015-08-11
DE60200289D1 (de) 2004-04-29
DE60200289T2 (de) 2005-02-17
CN1485624A (zh) 2004-03-31
EP1316808A1 (en) 2003-06-04

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Owner name: VERIGY (SINGAPORE) PTE LTD

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Patentee after: Verigy Pte Ltd Singapore

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Owner name: ADVANTEST (SINGAPORE) PTE. LTD.

Free format text: FORMER OWNER: VERIGY (SINGAPORE) PTE. LTD.

Effective date: 20120425

C41 Transfer of patent application or patent right or utility model
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Effective date of registration: 20120425

Address after: Singapore Singapore

Patentee after: Verigy Pte Ltd Singapore

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Patentee before: Inovys Corp.

ASS Succession or assignment of patent right

Owner name: ADVANTEST CORP.

Free format text: FORMER OWNER: ADVANTEST (CHINA) CO., LTD.

Effective date: 20150430

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150430

Address after: Tokyo, Japan, Japan

Patentee after: ADVANTEST CORP

Address before: Singapore Singapore

Patentee before: Verigy Pte Ltd Singapore

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070530

Termination date: 20200717