JP2004056154A - 酸化防止膜を挿入する誘電膜蒸着方法 - Google Patents

酸化防止膜を挿入する誘電膜蒸着方法 Download PDF

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JP2004056154A
JP2004056154A JP2003277324A JP2003277324A JP2004056154A JP 2004056154 A JP2004056154 A JP 2004056154A JP 2003277324 A JP2003277324 A JP 2003277324A JP 2003277324 A JP2003277324 A JP 2003277324A JP 2004056154 A JP2004056154 A JP 2004056154A
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dielectric film
film
dielectric
deposition method
antioxidant
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JP4596756B2 (ja
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Shoken Ri
李　正　賢
▼閃▲　ヨセプ
Yo-Sep Min
▲曹▼　永　眞
Young-Jin Cho
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

【課題】　シリコンと誘電膜との間に、低誘電層の発生を抑制して高い誘電定数と低い漏れ電流の特性とを有する誘電膜を蒸着する方法を提供すること。
【解決手段】　基板上に誘電膜を蒸着する方法において、基板と誘電膜の界面と、誘電膜間の界面とに下部電極の酸化及び拡散を防止する酸化防止膜を挿入して蒸着することを特徴とする誘電膜蒸着法を課題の解決手段とする。これにより低い漏れ電流と高静電容量との特性を有するキャパシタを具現でき、格子定数を調節して誘電定数を調節できるため、大面積基板に高い誘電定数を有する多層膜構造を具現できる。
【選択図】図３Ｄ

Description

　本発明は、誘電膜蒸着方法に係り、殊に下部電極の酸化と拡散とを防止する防止膜を利用した誘電膜蒸着法に関する。
　高誘電定数を有する誘電膜は、メモリ素子のキャパシタやゲート絶縁層以外に、大面積のガリウムヒ素（ＧａＡｓ）基板形成のためのバッファ層などとして利用されている。特に、この高誘電定数を有する誘電膜は、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）のようなメモリのキャパシタに多く利用されており、メモリの高集積化にともない、半導体素子を、限られた一定面積の基板上で形成するために、さらに高静電容量を有するキャパシタを実現する必要性が高まっている。
　キャパシタは、所定の静電容量を得るために、対面させて形成した導電体と、その間に形成される誘電膜とから構成される。キャパシタの静電容量は、導電体の有効面積と誘電膜の誘電率とに比例して、誘電膜の厚さに反比例するので、高誘電率の物質を誘電膜として選択し、その厚さを薄くして、有効面積を広げることで高静電容量を有するキャパシタを実現できる。ＤＲＡＭのようなメモリ素子では、幅が狭く、高い柱状の下部電極を有するキャパシタを形成することで、その表面に蒸着される誘電膜の有効面積を広げている。
　ここで、図１は、Ｓｉ基板上にストロンチウムチタネート（ＳＴＯ）誘電膜を蒸着して形成した多層膜を透過型電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）で撮った写真である。図１を参照して、Ｓｉ基板（Ｓｉ　Ｓｕｂｓｔｒａｔｅ）上にＳＴＯ誘電膜を蒸着する場合、Ｓｉ基板は酸化膜蒸着工程中に導入される酸素により容易に酸化されて、その上面にＳｉＯ2誘電膜が形成され、非晶質ＳｉＯ2（Ａｍｏｒｐｈｏｕｓ　ＳＴＯ）となり、当初のＳＴＯ誘電膜は、格子配列が崩れてしまう。さらに、ＳＴＯ誘電膜において、蒸着後に、後続熱処理工程によってＳｉの一部が拡散することで、結晶質ＳＴＯ誘電膜が破壊される。この結果、図１に示すような、Ｓｉ基板上にＳｉＯ2誘電膜とＳＴＯ誘電膜とが順番に配列されたキャパシタは、ＳＴＯ誘電膜よりなるキャパシタとＳｉＯ2誘電膜よりなるキャパシタとが直列に連結された構造となり、キャパシタの全体的な静電容量は結果的に減少し、キャパシタの電気的な特性は悪化してしまう。
　このような問題点を克服するために、Ｓｉ基板上にＲｕまたはＴｉＮのような金属電極を蒸着した後で誘電膜を蒸着する方法が最近研究されている。図２は、Ｓｉ基板上にＴｉＮとＲｕ金属電極を蒸着した後で、ＳＴＯ誘電膜を蒸着する場合に、金属の含有量に対する酸素の比率（Ｏ2／（Ｔｉ＋Ａｌ＋Ｒｕ＋Ｎ））と各金属の活性度との関係を示したグラフである。
　図２を参照すると、Ｒｕは、誘電膜蒸着の酸化雰囲気において活性度が高く、容易にＲｕＯ2に変質するため、高温で熱処理工程を行うことができない。また、ＳｉとＲｕとの間に位置するＴｉＮが、次に示す化学式の反応により、ＴｉＯ2に変化して活性度が急激に低下することと、構造的に容易に破損して加工性が著しく悪いため、ＴｉＮを用いて７０ｎｍ以下の厚さを有する柱状のキャパシタを製作することは難しい。
　２ＴｉＮ＋２Ｏ2→２ＴｉＯ2＋Ｎ2
　また、ＤＲＡＭのようなメモリ素子に用いられるキャパシタは、少量の電荷を保持するため、非常に弱い漏れ電流にも情報が損失する可能性があり、このような漏れ電流を防止できる誘電膜蒸着方法が要求されている。
　従って、本発明の課題は、前記した従来技術の問題点を改善することであり、シリコンと誘電膜との間に、低誘電層の発生を抑制し、高い誘電定数と低い漏れ電流の特性とを有する誘電膜を蒸着する方法を提供することである。
　前記技術的課題を達成するために本発明は、基板上に多層誘電膜を蒸着する方法において、前記基板に第１酸化防止膜を形成する段階と、前記第１酸化防止膜上に第１誘電膜を形成する段階と、前記第１誘電膜上に第２酸化防止膜を形成する段階と、前記第２酸化防止膜上に複数の誘電膜を形成する段階とを含み、前記複数の誘電膜の各膜と隣接する誘電膜の界面に複数の酸化防止膜を配することを特徴とする誘電膜蒸着法を提供する。前記酸化防止膜は３、４及び５族金属酸化膜のいずれか一つを選択して形成され、特に前記金属
酸化膜はＡｌ2Ｏ3、ＴａＯ、ＴｉＯ2、ＨｆＯ2及びＺｒＯ2の少なくとも一つを選択して形成することが望ましい。
　ここで、前記誘電膜を蒸着した後で熱処理を行い、前記酸化防止膜の金属を、前記誘電膜に拡散させて除去することが望ましく、この熱処理時に７００℃以下の温度となるように熱を供給することが望ましい。
　前記誘電膜と前記酸化防止膜とは単原子層蒸着法を利用して蒸着し、前記酸化防止膜は原子層蒸着（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を利用して蒸着する。
　前記誘電膜は、ストロンチウムチタネート（ＳＴＯ）、バリウムチタネート（ＢＴＯ）、バリウムストロンチウムチタネート（ＢＳＴ）、リードランタニウムチタネート（ＰＬＴ）、リードタンタリウムジルコニウム（ＰＬＺ）及びストロンチウムビスマスタンタライト（ＳＢＴ）のいずれか一つを選択して形成される。
　これにより、酸化防止膜を基板と誘電膜との間及び誘電膜と誘電膜との間に蒸着することにより、Ｓｉ基板の酸化を防止してＳｉＯ2のような低誘電層の発生を抑制でき、高い誘電定数と低い漏れ電流の特性とを有する多層膜構造を実現できる。
　本発明に係る誘電膜蒸着方法によると、誘電膜の格子定数を調節して低い漏れ電流の特性と高静電容量とを有するキャパシタ及びゲート絶縁層を具現でき、結晶の面間距離を調節することで、例えば大面積のＧａＡｓ基板を製造することができる。
　以下、本発明の実施の形態における誘電膜蒸着方法を、図面を参照して詳細に説明する。
　初めに、図３Ａないし図３Ｄは、本実施の形態の誘電膜蒸着方法を説明する工程図である。まず、図３Ａに示すように、基板１１の上部に酸化防止膜１０を蒸着した後で、図３Ｂに示すように第１誘電膜１３を蒸着し、その後、再び酸化防止膜１０を蒸着する。次に、図３Ｃに示すように、酸化防止膜１０の上面に第２誘電膜１５を蒸着して、再び酸化防止膜１０を蒸着し、図３Ｄに示すように、その上面に第３誘電膜１７を蒸着して、３層の誘電層を有する多層膜構造を形成する。
　本実施の形態の誘電膜蒸着方法は、基板と誘電膜との間、及び誘電膜と誘電膜との間に酸化防止膜を挿入することにより、基板及び誘電膜の酸化を防止することを特徴としている。ここで、第１誘電膜ないし第３誘電膜１３、１５、１７は、同じ物質または異なる物質より形成できる。なお、本実施の形態の多層構造よりも多層の誘電膜を有する多層構造を形成することも可能である。
　酸化防止膜１０としては、基板１１を形成する物質より容易に酸化される物質が誘電膜として使用され、３、４及び５族金属や、これらの金属の酸化物を使用できる。例えば、
Ａｌ、Ｔａ、Ｔｉ、Ｈｆ及びＺｒやＡｌ2Ｏ3、ＴａＯ、ＴｉＯ2、ＨｆＯ2及びＺｒＯ2のような物質を使用でき、その厚さは、利用される素子の構造により、数十Å（数ｎｍ）ないし数百Å（数十ｎｍ）になるように任意に最適化されて形成される。なお、酸化防止膜１０はＡＬＤ法を利用して蒸着される。このＡＬＤ法は、単原子層の化学吸着及び脱離を利用した薄膜蒸着技術であり、各反応物質を個別に分離してパルス状でチャンバに供給し、基板表面に反応物質の表面飽和反応による化学吸着と脱離とを利用して蒸着する技術である。
　第１誘電膜ないし第３誘電膜１３、１５、１７は高い誘電定数Ｋを有する誘電物質により形成され、例えばＳＴＯ、ＰＬＴ、ＢＴＯ、ＢＳＴ、ＰＬＺ及びＳＢＴのような物質を使用できる。ここで、誘電膜を蒸着する方法は、同じくＡＬＤ法を用いる。
　本実施の形態の誘電膜蒸着法では、基板１１の上部に酸化防止膜１０が界面に挿入されて誘電膜が蒸着された図３Ｄに示した多層構造を形成した後で、高温酸化雰囲気による熱処理工程をさらに含む。熱処理工程をさらに行うことで、酸化防止膜１０の金属元素が、第１誘電膜ないし第３誘電膜１３、１５、１７に拡散し、冷却されつつ結晶化して、第１誘電膜ないし第３誘電膜１３、１５、１７の格子定数が変化する。酸化防止膜１０の金属元素のイオン半径が小さい場合には、第１誘電膜ないし第３誘電膜１３、１５、１７の格子定数は小さくなり、その逆の場合には、第１誘電膜ないし第３誘電膜１３、１５、１７の格子定数は大きくなる。本実施の形態の誘電膜蒸着法において、ＳＴＯ誘電膜の格子定数は（ａ＝０．３９０５ｎｍ）であるが、熱処理によりＨｆ元素が拡散することで、熱処理後には（ａ＝０．３９２３ｎｍ）と大きくなる。
　ここで、図４Ａは、本実施の形態の誘電膜蒸着方法により蒸着されたＳＴＯ／ＨｆＯ2／ＳＴＯの多層膜構造のＴＥＭ写真であり、図４Ｂは図４Ａに示した多層膜構造を熱処理した後で、変化した構造を撮影したＴＥＭ写真である。
　図４Ａを参照すると、ＳＴＯ間にＨｆＯ2が挿入されているが、熱処理を行うことで、図４Ｂに示すように、ＨｆＯ2膜が誘電膜に拡散して消滅していることが分かる。ここで、ＳＴＯ誘電膜の結晶面の距離は、格子構造で熱処理前の０．３９０５ｎｍから熱処理後の０．３９２３ｎｍと変化する。この変化した結晶膜はＳＴＯ膜の上面にＧａＡｓのような膜を蒸着する場合に、格子定数の非適合による応力を緩和することができる。ここで、ＳＴＯ誘電膜の上面に酸化防止膜を挿入した後でＧａＡｓ膜を蒸着させた構造は、光記録媒体を製造する場合に使用できる。
　ここで、例えば、図５は、本実施の形態の誘電膜蒸着方法により蒸着された多層膜構造４０を有するキャパシタ３０が二つ配列されたＤＲＡＭを簡略に示した断面図である。図５を参照すると、このＤＲＡＭは、２つのトランジスタ５４と、２つのキャパシタ３０とを備える。トランジスタ５４は、ソース電極Ｓ、ドレーン電極Ｄ及びゲート電極５７から構成され、ゲート電極５７の上面にはストライプ状に配列されたワードライン５９と、２つのゲート電極５７間に配置されたビットライン５８とが形成されている。
　さらに詳細に説明すると、基板３１の表面に、所定の深さでソース電極Ｓ及びドレーン電極Ｄが形成されており、ソース電極Ｓ及びドレーン電極Ｄの間にゲート電極５７が配置されている。ここで図６Ｂは、符号Ｂで示したトランジスタ５４を拡大した断面図であるが、図６Ｂを参照すると、ゲート電極５７と基板３１との間には、絶縁層として複数の誘電膜５３、５５と複数の酸化防止膜５１とが交互して積層されている。また、絶縁層３３の内部には導電性プラグ３５が設けられ、ソース電極Ｓが接触して導電性プラグ３５の上面には柱状の下部電極３７が位置してその上面には多層膜構造４０が蒸着され、さらにその上面には上部電極３９が蒸着される。
　ここで、図６Ａは図５の符号Ａで示した部分を拡大した断面図であり、キャパシタ３０の多層膜構造４０を拡大して示している。下部電極３７の上面には酸化防止膜４１が蒸着され、順に第１誘電膜４３、酸化防止膜４１、第２誘電膜４５が積層されて多層膜構造４０を形成し、最後に、その上面に上部電極３９が蒸着されてキャパシタを形成している。
　また、図６Ｂを参照すると、ソース電極Ｓとドレーン電極との間にはワードライン５９が配置され、その底面にはゲート電極５７が形成され、ゲート電極５７と基板３１との間には酸化防止膜５１、第１誘電膜５３、酸化防止膜５１及び第２誘電膜５５が順番に蒸着されて多層膜構造５０を形成している。このような酸化防止膜５１と誘電膜５３、５７とが交互して形成された多層誘電膜構造を備えるキャパシタは、漏れ電流が減少して静電容量が増加する特性を示す。
　ここで、図７は、本実施の形態の誘電膜蒸着方法において、酸化防止膜としてＡｌＯ膜を使用し、誘電膜としてＳＴＯ膜を使用する場合の電圧の変化に対する漏れ電流の変化を示すグラフである。図７を参照すると、ＳＴＯ誘電膜の厚さを２２．５ｎｍ（２２５Å）に維持した時に、ＡｌＯ酸化防止膜を１、２、３、５ｎｍ（１０、２０、３０、５０Å）と変化させて蒸着した場合の漏れ電流は、電圧が−４Ｖ〜３Ｖの範囲である場合、１０-7Ａ／ｃｍ2（基準漏れ電流）より小さな値を示している。この値はＡｌＯ酸化防止膜（ＡｌＯ ５０ｒｅｆｅｒｅｎｃｅ）だけを用いた場合の電圧の変化に対する最小漏れ電流の値と大差ない値であって、漏れ電流がかなり減少していることが分かる。
　次に、図８は、本実施の形態の誘電膜蒸着法において、酸化防止膜としてＡｌＯ膜を使用し、誘電膜としてＳＴＯ膜を使用した場合に、ＡｌＯの厚さの変化に対する静電容量の変化を示すグラフである。図８に示したグラフにおいて、Ｘ軸は、ＡｌＯの厚さを示し、Ｙ軸はＳｉＯ2の厚さに換算した静電容量値を示している。ここで、ＳｉＯ2の厚さが２０である場合を基準静電容量の厚さと設定すると、ＡｌＯの厚さを２０Å（２ｎｍ）以下に蒸着した場合では、多層膜構造の換算厚さは基準静電容量の厚さより薄くなるため、基準静電容量より静電容量が大きくなる。これは式１に示すように静電容量Ｃが厚さｄとは反比例の関係にあるためである。
　ここで、εは誘電率、ｓはキャパシタの面積を示す。
　本実施の形態の誘電膜蒸着方法を用いて蒸着された多層膜構造は、低い漏れ電流の特性と高い静電容量とを示すので、高性能が要求されるメモリ素子、光記録媒体など多様な電子素子、光素子に利用することが可能である。
　なお、前記した説明の中で、多くの事項が具体的に記載されているが、それらは発明の範囲を限定するものではなく、望ましい一実施の形態として解釈さるべきである。本発明の範囲は前記した実施の形態により定められるのではなく、特許請求の範囲に記載された技術的思により定められる。
　本発明に係る誘電膜蒸着方法を用いて蒸着された多層膜構造は、低い漏れ電流の特性と高静電容量とを示すので、高性能が要求されるメモリ素子、光記録媒体など多様な電子素子、光素子に用いることが可能である。
Ｓｉ基板上にＳｒＴｉＯ3を蒸着した多層膜構造のＴＥＭ写真である。 従来の金属配線を利用して誘電膜蒸着を行う場合に各物質についての活性度を示したグラフである。 本発明の実施の形態の誘電膜蒸着方法において、基板上に酸化防止膜を蒸着させた図である。 図３Ａに示した積層構造の上部に、第１誘電膜と、酸化防止膜とを蒸着させた図である。 図３Ｂに示した積層構造の上部に、第２誘電膜と、酸化防止膜とを蒸着させた図である。 図３Ｃに示した積層構造の上部に、第３誘電膜を蒸着させた図である。 本発明の実施の形態の誘電膜蒸着法を使用する前のＳＴＯ／ＨｆＯ2／ＳＴＯの多層膜構造を撮ったＴＥＭ写真である。 図４Ａに示された多層膜構造を７００℃で熱処理した後で変化された多層薄膜構造を撮ったＴＥＭ写真である。 本発明の実施例による誘電膜蒸着法により誘電膜が蒸着されたキャパシタを備えるＤＲＡＭ構造を示した断面図である。 図５の符号Ａの部分を拡大した断面図である。 図５の符号Ｂの部分を拡大した断面図である。 本発明の実施の形態の誘電膜蒸着法により蒸着されたＡｌＯ／ＳＴＯの多層膜構造において電圧の変化による漏れ電流の変化を示したグラフである。 本発明の実施の形態の誘電膜蒸着法により蒸着されたＡｌＯ／ＳＴＯの多層膜構造においてＡｌＯの厚さの変化による静電容量の変化を示したグラフである。
符号の説明
　１０　　酸化防止膜
　１１　　基板
　１３　　第１誘電膜
　１５　　第２誘電膜
　１７　　第３誘電膜

Claims (8)

  1. 　基板上に多層の誘電膜を蒸着する方法において、
    　前記基板に酸化防止膜を形成する段階と、
    　前記酸化防止膜上に複数の誘電膜を形成する段階と、
    　前記複数の誘電膜の各膜と隣接する誘電膜の境界面に、複数の酸化防止膜を配置すること、
    　を特徴とする誘電膜蒸着法。
  2. 　前記酸化防止膜は、３、４及び５族金属酸化膜のうち一つを選択して形成すること、
    　を特徴とする請求項１に記載の誘電膜蒸着法。
  3. 　前記金属酸化膜は、Ａｌ2Ｏ3、ＴａＯ、ＴｉＯ2、ＨｆＯ2及びＺｒＯ2のいずれか一つであること、
    　を特徴とする請求項２に記載の誘電膜蒸着法。
  4. 　前記誘電膜を蒸着した後で熱処理し、前記酸化防止膜の金属を前記誘電膜に拡散させて除去すること、
    　を特徴とする請求項１ないし請求項３のいずれか１項に記載の誘電膜蒸着法。
  5. 　前記熱処理時に、７００℃以下の温度になるように熱を供給すること、
    　を特徴とする請求項４に記載の誘電膜蒸着法。
  6. 　前記誘電膜は、単原子層蒸着法で蒸着すること、
    　を特徴とする請求項１に記載の誘電膜蒸着法。
  7. 　前記酸化防止膜は、単原子層蒸着法で蒸着すること、
    　を特徴とする請求項１に記載の誘電膜蒸着法。
  8. 　前記誘電膜は、ストロンチウムチタネート（ＳＴＯ）、バリウムチタネート（ＢＴＯ）、バリウムストロンチウムチタネート（ＢＳＴ）、リードランタニウムチタネート（ＰＬＴ）、リードタンタリウムジルコニウム（ＰＬＺ）及びストロンチウムビスマスタンタライト（ＳＢＴ）のうちいずれか一つで形成すること、
    　を特徴とする請求項１に記載の誘電膜蒸着法。
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