JP2004031937A - 半導体デバイス障壁層 - Google Patents

半導体デバイス障壁層 Download PDF

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Publication number
JP2004031937A
JP2004031937A JP2003142780A JP2003142780A JP2004031937A JP 2004031937 A JP2004031937 A JP 2004031937A JP 2003142780 A JP2003142780 A JP 2003142780A JP 2003142780 A JP2003142780 A JP 2003142780A JP 2004031937 A JP2004031937 A JP 2004031937A
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JP
Japan
Prior art keywords
dielectric material
thin film
semiconductor device
silicon nitride
recess
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Pending
Application number
JP2003142780A
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English (en)
Japanese (ja)
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JP2004031937A5 (enExample
Inventor
Sailesh M Merchant
サイレッシュ　マンシン　マーチャント
Isaiah O Oladeji
アイサイアー　オー．オラデジ
Seong Jin Koh
セオン　ジン　コー
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Agere Systems LLC
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Agere Systems LLC
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Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of JP2004031937A publication Critical patent/JP2004031937A/ja
Publication of JP2004031937A5 publication Critical patent/JP2004031937A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003142780A 2002-05-21 2003-05-21 半導体デバイス障壁層 Pending JP2004031937A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/153,231 US6686662B2 (en) 2002-05-21 2002-05-21 Semiconductor device barrier layer

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011160546A Division JP2011205155A (ja) 2002-05-21 2011-07-22 半導体デバイス障壁層

Publications (2)

Publication Number Publication Date
JP2004031937A true JP2004031937A (ja) 2004-01-29
JP2004031937A5 JP2004031937A5 (enExample) 2006-07-06

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
JP2003142780A Pending JP2004031937A (ja) 2002-05-21 2003-05-21 半導体デバイス障壁層
JP2011160546A Pending JP2011205155A (ja) 2002-05-21 2011-07-22 半導体デバイス障壁層

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011160546A Pending JP2011205155A (ja) 2002-05-21 2011-07-22 半導体デバイス障壁層

Country Status (5)

Country Link
US (1) US6686662B2 (enExample)
JP (2) JP2004031937A (enExample)
KR (1) KR100977947B1 (enExample)
GB (1) GB2388959A (enExample)
TW (1) TW559951B (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462884B1 (ko) * 2002-08-21 2004-12-17 삼성전자주식회사 희생충진물질을 이용한 반도체 장치의 듀얼다마신배선형성방법
KR100523618B1 (ko) * 2002-12-30 2005-10-24 동부아남반도체 주식회사 반도체 장치의 콘택트 홀 형성 방법
US20040222527A1 (en) * 2003-05-06 2004-11-11 Dostalik William W. Dual damascene pattern liner
KR101048002B1 (ko) * 2003-12-26 2011-07-13 매그나칩 반도체 유한회사 반도체 소자의 장벽 금속층 형성방법
JP2005217162A (ja) * 2004-01-29 2005-08-11 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
KR100642633B1 (ko) * 2004-06-11 2006-11-10 삼성전자주식회사 엠아이엠 캐패시터들 및 그의 제조 방법
US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement
KR100715267B1 (ko) * 2005-06-09 2007-05-08 삼성전자주식회사 스택형 반도체 장치 및 그 제조 방법
US8415799B2 (en) * 2005-06-30 2013-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene interconnect in hybrid dielectric
US8134196B2 (en) * 2005-09-02 2012-03-13 Stats Chippac Ltd. Integrated circuit system with metal-insulator-metal circuit element
US20070052107A1 (en) * 2005-09-05 2007-03-08 Cheng-Ming Weng Multi-layered structure and fabricating method thereof and dual damascene structure, interconnect structure and capacitor
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7417321B2 (en) * 2005-12-30 2008-08-26 Taiwan Semiconductor Manufacturing Co., Ltd Via structure and process for forming the same
US7435674B2 (en) * 2006-03-27 2008-10-14 International Business Machines Corporation Dielectric interconnect structures and methods for forming the same
US9385034B2 (en) * 2007-04-11 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Carbonization of metal caps
KR100924546B1 (ko) * 2007-07-27 2009-11-02 주식회사 하이닉스반도체 반도체 소자의 금속배선 및 그의 형성방법
DE102007046851B4 (de) * 2007-09-29 2019-01-10 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterstruktur mit einem elektrisch leitfähigen Strukturelement und Verfahren zum Ausbilden einer Halbleiterstruktur
JP5331443B2 (ja) * 2008-10-29 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8283250B2 (en) 2008-12-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming a conductive via-in-via structure
JP5173863B2 (ja) * 2009-01-20 2013-04-03 パナソニック株式会社 半導体装置およびその製造方法
US8138605B2 (en) * 2009-10-26 2012-03-20 Alpha & Omega Semiconductor, Inc. Multiple layer barrier metal for device component formed in contact trench
US10269706B2 (en) * 2016-07-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9905459B1 (en) * 2016-09-01 2018-02-27 International Business Machines Corporation Neutral atom beam nitridation for copper interconnect
US11195748B2 (en) * 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US10964636B2 (en) * 2018-09-19 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure with low resistivity and method for forming the same
US11076492B2 (en) * 2018-12-17 2021-07-27 Averatek Corporation Three dimensional circuit formation
US12156331B2 (en) * 2021-03-25 2024-11-26 Intel Corporation Technologies for power tunnels on circuit boards
US12105163B2 (en) 2021-09-21 2024-10-01 Tdk Corporation Magnetic sensor
CN114267634A (zh) * 2021-12-21 2022-04-01 华虹半导体(无锡)有限公司 低通孔双大马士革结构的制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07307338A (ja) * 1993-10-29 1995-11-21 Toshiba Corp 半導体装置の製造方法および半導体装置
JPH10125783A (ja) * 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
JPH10335458A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
JPH1140671A (ja) * 1997-07-16 1999-02-12 Motorola Inc 半導体装置を形成するためのプロセス
JP2001035917A (ja) * 1999-07-19 2001-02-09 Hitachi Ltd 半導体装置およびその製造方法
US20020001952A1 (en) * 2000-02-25 2002-01-03 Chartered Semiconductor Manufacturing Ltd. Non metallic barrier formations for copper damascene type interconnects

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2946978B2 (ja) * 1991-11-29 1999-09-13 ソニー株式会社 配線形成方法
JP2728025B2 (ja) * 1995-04-13 1998-03-18 日本電気株式会社 半導体装置の製造方法
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US5668054A (en) 1996-01-11 1997-09-16 United Microelectronics Corporation Process for fabricating tantalum nitride diffusion barrier for copper matallization
US6037246A (en) * 1996-09-17 2000-03-14 Motorola Inc. Method of making a contact structure
US5940698A (en) 1997-12-01 1999-08-17 Advanced Micro Devices Method of making a semiconductor device having high performance gate electrode structure
US6294836B1 (en) 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6417094B1 (en) 1998-12-31 2002-07-09 Newport Fab, Llc Dual-damascene interconnect structures and methods of fabricating same
US6140231A (en) 1999-02-12 2000-10-31 Taiwan Semiconductor Manufacturing Company Robust diffusion barrier for Cu metallization
US6339258B1 (en) * 1999-07-02 2002-01-15 International Business Machines Corporation Low resistivity tantalum
US6140220A (en) * 1999-07-08 2000-10-31 Industrial Technology Institute Reseach Dual damascene process and structure with dielectric barrier layer
KR100436134B1 (ko) * 1999-12-30 2004-06-14 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
US6372636B1 (en) * 2000-06-05 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
KR100623332B1 (ko) * 2000-06-30 2006-09-11 매그나칩 반도체 유한회사 반도체소자의 금속배선 형성방법
US6531780B1 (en) * 2001-06-27 2003-03-11 Advanced Micro Devices, Inc. Via formation in integrated circuit interconnects
US6525428B1 (en) * 2002-06-28 2003-02-25 Advance Micro Devices, Inc. Graded low-k middle-etch stop layer for dual-inlaid patterning

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07307338A (ja) * 1993-10-29 1995-11-21 Toshiba Corp 半導体装置の製造方法および半導体装置
JPH10125783A (ja) * 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
JPH10335458A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
JPH1140671A (ja) * 1997-07-16 1999-02-12 Motorola Inc 半導体装置を形成するためのプロセス
JP2001035917A (ja) * 1999-07-19 2001-02-09 Hitachi Ltd 半導体装置およびその製造方法
US20020001952A1 (en) * 2000-02-25 2002-01-03 Chartered Semiconductor Manufacturing Ltd. Non metallic barrier formations for copper damascene type interconnects

Also Published As

Publication number Publication date
GB2388959A (en) 2003-11-26
JP2011205155A (ja) 2011-10-13
US20030218256A1 (en) 2003-11-27
KR100977947B1 (ko) 2010-08-24
KR20030091700A (ko) 2003-12-03
GB0220209D0 (en) 2002-10-09
TW559951B (en) 2003-11-01
US6686662B2 (en) 2004-02-03

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