JP2003520417A5 - - Google Patents

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Publication number
JP2003520417A5
JP2003520417A5 JP2000614502A JP2000614502A JP2003520417A5 JP 2003520417 A5 JP2003520417 A5 JP 2003520417A5 JP 2000614502 A JP2000614502 A JP 2000614502A JP 2000614502 A JP2000614502 A JP 2000614502A JP 2003520417 A5 JP2003520417 A5 JP 2003520417A5
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JP
Japan
Prior art keywords
substrate
forming
regions
silicide layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000614502A
Other languages
English (en)
Japanese (ja)
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JP4791635B2 (ja
JP2003520417A (ja
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Publication date
Priority claimed from US09/298,293 external-priority patent/US6117762A/en
Application filed filed Critical
Publication of JP2003520417A publication Critical patent/JP2003520417A/ja
Publication of JP2003520417A5 publication Critical patent/JP2003520417A5/ja
Application granted granted Critical
Publication of JP4791635B2 publication Critical patent/JP4791635B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000614502A 1999-04-23 2000-04-14 シリサイド層を用いてリバースエンジニエアリングから集積回路を保護する方法および装置 Expired - Fee Related JP4791635B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/298,293 1999-04-23
US09/298,293 US6117762A (en) 1999-04-23 1999-04-23 Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering
PCT/US2000/010106 WO2000065654A1 (en) 1999-04-23 2000-04-14 Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering

Publications (3)

Publication Number Publication Date
JP2003520417A JP2003520417A (ja) 2003-07-02
JP2003520417A5 true JP2003520417A5 (https=) 2007-06-07
JP4791635B2 JP4791635B2 (ja) 2011-10-12

Family

ID=23149876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000614502A Expired - Fee Related JP4791635B2 (ja) 1999-04-23 2000-04-14 シリサイド層を用いてリバースエンジニエアリングから集積回路を保護する方法および装置

Country Status (6)

Country Link
US (1) US6117762A (https=)
EP (1) EP1183729A1 (https=)
JP (1) JP4791635B2 (https=)
AU (1) AU4244000A (https=)
TW (1) TW586168B (https=)
WO (1) WO2000065654A1 (https=)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6459629B1 (en) * 2001-05-03 2002-10-01 Hrl Laboratories, Llc Memory with a bit line block and/or a word line block for preventing reverse engineering
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6897535B2 (en) * 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US6762464B2 (en) * 2002-09-17 2004-07-13 Intel Corporation N-p butting connections on SOI substrates
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6924552B2 (en) * 2002-10-21 2005-08-02 Hrl Laboratories, Llc Multilayered integrated circuit with extraneous conductive traces
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
WO2004055868A2 (en) * 2002-12-13 2004-07-01 Hrl Laboratories, Llc Integrated circuit modification using well implants
GB0410975D0 (en) 2004-05-17 2004-06-16 Nds Ltd Chip shielding system and method
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
DE102005028905A1 (de) * 2005-06-22 2006-12-28 Infineon Technologies Ag Transistorbauelement
US8168487B2 (en) * 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
JP5135992B2 (ja) * 2007-10-24 2013-02-06 ソニー株式会社 半導体装置およびその製造方法
DE102008014750A1 (de) 2008-03-18 2009-10-01 Siemens Aktiengesellschaft Gehäuse zum Schutz vor Nachbau
US8510700B2 (en) 2009-02-24 2013-08-13 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
US9735781B2 (en) 2009-02-24 2017-08-15 Syphermedia International, Inc. Physically unclonable camouflage structure and methods for fabricating same
US10691860B2 (en) 2009-02-24 2020-06-23 Rambus Inc. Secure logic locking and configuration with camouflaged programmable micro netlists
US8418091B2 (en) 2009-02-24 2013-04-09 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit
US8151235B2 (en) * 2009-02-24 2012-04-03 Syphermedia International, Inc. Camouflaging a standard cell based integrated circuit
US8111089B2 (en) * 2009-05-28 2012-02-07 Syphermedia International, Inc. Building block for a secure CMOS logic cell library
US9218511B2 (en) 2011-06-07 2015-12-22 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US8975748B1 (en) 2011-06-07 2015-03-10 Secure Silicon Layer, Inc. Semiconductor device having features to prevent reverse engineering
US9287879B2 (en) * 2011-06-07 2016-03-15 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US9437555B2 (en) 2011-06-07 2016-09-06 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US9479176B1 (en) 2013-12-09 2016-10-25 Rambus Inc. Methods and circuits for protecting integrated circuits from reverse engineering
DE102016124590B4 (de) 2016-12-16 2023-12-28 Infineon Technologies Ag Halbleiterchip
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4267578A (en) * 1974-08-26 1981-05-12 Texas Instruments Incorporated Calculator system with anti-theft feature
US4139864A (en) * 1976-01-14 1979-02-13 Schulman Lawrence S Security system for a solid state device
US4583011A (en) * 1983-11-01 1986-04-15 Standard Microsystems Corp. Circuit to prevent pirating of an MOS circuit
JP2755613B2 (ja) 1988-09-26 1998-05-20 株式会社東芝 半導体装置
EP0463373A3 (en) 1990-06-29 1992-03-25 Texas Instruments Incorporated Local interconnect using a material comprising tungsten
JP2978736B2 (ja) * 1994-06-21 1999-11-15 日本電気株式会社 半導体装置の製造方法
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
JPH1056082A (ja) * 1996-08-07 1998-02-24 Mitsubishi Electric Corp 半導体集積回路装置及びその製造方法
US5976943A (en) * 1996-12-27 1999-11-02 Vlsi Technology, Inc. Method for bi-layer programmable resistor
US6326675B1 (en) 1999-03-18 2001-12-04 Philips Semiconductor, Inc. Semiconductor device with transparent link area for silicide applications and fabrication thereof

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