WO2002025701A3 - Body-tied silicon on insulator semiconductor device structure and method therefor - Google Patents

Body-tied silicon on insulator semiconductor device structure and method therefor Download PDF

Info

Publication number
WO2002025701A3
WO2002025701A3 PCT/US2001/027704 US0127704W WO0225701A3 WO 2002025701 A3 WO2002025701 A3 WO 2002025701A3 US 0127704 W US0127704 W US 0127704W WO 0225701 A3 WO0225701 A3 WO 0225701A3
Authority
WO
WIPO (PCT)
Prior art keywords
region
trench isolation
silicon
device structure
soi
Prior art date
Application number
PCT/US2001/027704
Other languages
French (fr)
Other versions
WO2002025701A2 (en
Inventor
Byoung W Min
Michael A Mendicino
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001288845A priority Critical patent/AU2001288845A1/en
Publication of WO2002025701A2 publication Critical patent/WO2002025701A2/en
Publication of WO2002025701A3 publication Critical patent/WO2002025701A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

A silicon on insulator (SOI) device structure and method therefore in which the SOI device structure utilizes a conductive body contact region (220) under a partial trench isolation region (250) to connect a doped region (320), which is a conductive area, with the body region (380) of the device such that the desired potential within the body region (380) can be achieved. This is accomplished by patterning the silicon on insulator (SOI) substrate and etching away the portion of the substrate within which the partial trench isolation is to be formed. Following the etching operation, an implant step dopes the remaining portion of the silicon film underlying the partial trench isolation region (250) to achieve the desired conductivity. Full trench isolation regions (240) are then patterned and formed. Subsequent formation of contacts (710, 720) and other layers of interconnect (750) complete formation of the SOI device.
PCT/US2001/027704 2000-09-19 2001-09-07 Body-tied silicon on insulator semiconductor device structure and method therefor WO2002025701A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001288845A AU2001288845A1 (en) 2000-09-19 2001-09-07 Body-tied silicon on insulator semiconductor device structure and method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66555000A 2000-09-19 2000-09-19
US09/665,550 2000-09-19

Publications (2)

Publication Number Publication Date
WO2002025701A2 WO2002025701A2 (en) 2002-03-28
WO2002025701A3 true WO2002025701A3 (en) 2002-10-10

Family

ID=24670554

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/027704 WO2002025701A2 (en) 2000-09-19 2001-09-07 Body-tied silicon on insulator semiconductor device structure and method therefor

Country Status (3)

Country Link
AU (1) AU2001288845A1 (en)
TW (1) TW506078B (en)
WO (1) WO2002025701A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732287B2 (en) 2006-05-02 2010-06-08 Honeywell International Inc. Method of forming a body-tie
US7964897B2 (en) 2008-07-22 2011-06-21 Honeywell International Inc. Direct contact to area efficient body tie process flow
JP5736808B2 (en) * 2011-02-02 2015-06-17 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US8946819B2 (en) * 2013-05-08 2015-02-03 Globalfoundries Singapore Pte. Ltd. Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246562A (en) * 1996-03-14 1997-09-19 Nec Corp Semiconductor device of soi structure
JPH10242470A (en) * 1997-02-28 1998-09-11 Toshiba Corp Semiconductor device and fabrication thereof
EP0989613A1 (en) * 1998-08-29 2000-03-29 International Business Machines Corporation SOI transistor with body contact and method of forming same
DE10054098A1 (en) * 2000-03-24 2001-10-04 Mitsubishi Electric Corp Semiconductor device with element-insulating insulation films, has stacked structure comprising semiconductor substrate, insulating layer, and semiconductor layer in given sequence

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246562A (en) * 1996-03-14 1997-09-19 Nec Corp Semiconductor device of soi structure
JPH10242470A (en) * 1997-02-28 1998-09-11 Toshiba Corp Semiconductor device and fabrication thereof
EP0989613A1 (en) * 1998-08-29 2000-03-29 International Business Machines Corporation SOI transistor with body contact and method of forming same
DE10054098A1 (en) * 2000-03-24 2001-10-04 Mitsubishi Electric Corp Semiconductor device with element-insulating insulation films, has stacked structure comprising semiconductor substrate, insulating layer, and semiconductor layer in given sequence

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 14 31 December 1998 (1998-12-31) *

Also Published As

Publication number Publication date
WO2002025701A2 (en) 2002-03-28
TW506078B (en) 2002-10-11
AU2001288845A1 (en) 2002-04-02

Similar Documents

Publication Publication Date Title
US7704811B2 (en) Sub-lithographics opening for back contact or back gate
US20010029067A1 (en) Semiconductor device and manufacturing method thereof
EP1017096A3 (en) Method of fabricating semiconductor memory device
KR970054334A (en) Thin film transistor and its manufacturing method
JPH02256267A (en) Film soi c-mos element and its manufacture
WO2002035606A1 (en) Semiconductor device and its production method
JPH1074921A (en) Semiconductor device and manufacturing method thereof
WO2002103785A3 (en) Cmos process
WO2002025701A3 (en) Body-tied silicon on insulator semiconductor device structure and method therefor
JP2003243666A (en) Structure of semiconductor integrated circuit and method of manufacturing the same
KR960042931A (en) Manufacturing Method of Semiconductor Device Having SOI Structure
WO2003044853A3 (en) Substrate contact in soi and method therefor
JP3932443B2 (en) Semiconductor element
KR20010014771A (en) Semiconductor device
US20010001483A1 (en) Dynamic threshold voltage devices with low gate to substrate resistance
TW200516713A (en) Method fabricating a memory device having a self-aligned contact
KR100372820B1 (en) Double silicon mosfet and method of manufacturing the same
JP4124553B2 (en) Semiconductor device
JPH033272A (en) Semiconductor device
US6521517B1 (en) Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer
KR100318318B1 (en) Manufacturing Method for Cell of Semiconductor Memory Device
KR970072295A (en) Method for forming a separation film of a semiconductor element
KR100265327B1 (en) Soi device without floating body effect and method for fabricating the same
WO2001071802A3 (en) Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers
KR100477786B1 (en) Method for forming contact in semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP