JPH09246562A - Semiconductor device of soi structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the drop of junction breakdown strength between a body contact area and source/drain regions. SOLUTION: An SOI structure of semiconductor device, which includes a MOS-type semiconductor element having a channel region 3, a source region 4, and a drain region 5 made on a first insulator layer 2, is equipped with a body contact region 9, which is made on the first insulator layer 2, and a specified path 8 which electrically connects the channel region 3 with the body contact region 9, being made on the first insulator layer 2. Then, between the body contact region 9 and the source/drain regions 4 and 5, a third insulator layer 10 is interposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a so-called SOI (Silicon on In).
MOS (Metal Oxid) with a sulator structure
The present invention relates to an eSemiconductor type semiconductor device.

[0002]

2. Description of the Related Art The SOI technology for forming a single crystal silicon layer on an insulating layer is a semiconductor process technology that enables high speed, low power consumption, high density and high reliability of a semiconductor integrated circuit. .

SOI manufactured using this SOI technology
A MOS type semiconductor device having a structure generally has a structure as shown in FIG.

That is, a MOS type semiconductor device having an SOI structure has a single crystal silicon substrate 1, a first insulator layer 2 provided on the single crystal silicon substrate 1, and a predetermined insulator on the first insulator layer 2. Conductivity type channel region 3 provided in the region
And a second conductive type first semiconductor region (source) provided on the first insulator layer 2 so as to be adjacent to one end of the channel region 3 in the channel length direction (left and right direction in FIG. 11). Region 4), and a second conductivity type second semiconductor region (drain region) 5 provided on the first insulator layer 2 so as to be adjacent to the other end of the channel region in the channel length direction. The second insulating layer (gate insulating film) 6 formed on the channel region 3 and the gate electrode 7 formed on the gate insulating film 6.

Hereinafter, each component will be specifically described with the first conductivity type being p-type and the second conductivity type being n-type.

Generally, it is relatively easy to grow polycrystalline silicon on an insulating layer, but it is difficult to grow single crystal silicon. Therefore, SIMOX (S
separation by Implanted Ox
ygen) method or bonding method such as SO
I technology will be used.

Here, the SIMOX method is a method in which oxygen ions are implanted into a single crystal silicon substrate, and a single crystal silicon layer is left on the surface to form an insulator layer composed of a SiO ₂ layer inside the single crystal silicon substrate. Is.

In addition, the bonding method is to form a thermal oxide film on one or both of two single crystal substrates, and after bonding these, one of the single crystal substrates is thinly cut to form an element layer. Is the way.

When a single crystal silicon layer is formed on the first insulator layer 2 by using the SOI technique, impurities of each conductivity type are injected into the formed single crystal silicon layer, and the channel region 3 is formed. , The source region 4 and the drain region 5 are formed.

Here, to give an example, the channel region 3
Contains a p-type impurity, boron, at a relatively low concentration, for example, about 10 ¹⁵ to 10 ¹⁷ / cm ³ , and the source region 4
The drain region 5 contains arsenic or phosphorus, which is an n-type impurity, at a relatively high concentration, for example, 10 ¹⁹ to 10 ²¹ / cm ^3.
Includes the degree.

An SOI structure MO having such a structure
The S-type semiconductor element further includes a MOS type semiconductor element having a thick film SOI structure and a thin film SOI, depending on the thickness of the single crystal silicon layer.
The structure is classified into a MOS type semiconductor device.

Here, the film thickness of the single crystal silicon layer (channel region 3, source region 4, drain region 5) of the MOS semiconductor element having a thick film SOI structure is, for example, about 10,000 ×.
The thickness is 10 ⁻⁸ cm or more, and the thickness of the MOS type semiconductor device having the thin film SOI structure is, for example, about 300 to 2000 × 10 ⁻⁸ c.
m.

This thin film SOI structure MOS type semiconductor device has many characteristics as compared with a normal SOI structure MOS type semiconductor device. For example, one of its characteristics is that the parasitic capacitance is smaller than that of a bulk type MOS semiconductor element. This is a bulk MO
This is because not only the junction capacitance of the source / drain region can be reduced as compared with the S-type semiconductor element, but also the wiring capacitance between the substrate and the substrate can be reduced.

Further, in the MOS type semiconductor element having the thin film SOI structure, since the current path is not formed in the deep layer on the substrate side, it is strong against the so-called punch through phenomenon.

However, the MOS type semiconductor device having the thin film SOI structure has various advantages as described above,
There is a problem of floating substrate effect.

The substrate floating effect causes various problems such as a decrease in drain breakdown voltage and a kink in current-voltage characteristics due to excess carriers accumulated in the channel region.

Therefore, conventionally, a body contact region electrically connected to the channel region 3 through a predetermined path is provided,
By extracting the excess carriers accumulated in the channel region from this body contact region, the substrate floating effect is suppressed.

S having a body contact region of this kind
A MOS type semiconductor device having an OI structure is disclosed in Japanese Patent Laid-Open No. 57-
27068 (hereinafter referred to as Cited Example 1) and the conventional example (hereinafter referred to as Cited Example 2) cited in the publication, JP-A-4-349.
No. 80 (hereinafter referred to as Cited Example 3) and Japanese Patent Laid-Open No. 5-1147.
No. 34 (hereinafter, referred to as Reference Example 4) is disclosed.

Each of the cited examples will be described below with reference to the drawings.

As shown in FIGS. 12 and 13, the reference example 1 has a p ⁻ type channel region 3 and an n ⁺ type source region 4 provided so as to sandwich the p ⁻ type channel region 3.
And n ⁺ type drain region 5 and n ⁺ type source region 4
P ⁺ type body contact region 9 provided adjacent to
And a predetermined p-type path 8 which is provided so as to surround the whole and electrically connects the p ⁻ -type channel region 3 and the p ⁺ -type body contact region 9, and is accumulated in the channel region 3. The surplus carriers thus taken out are taken out from the body contact region 9 via a predetermined path 8.

Further, in the second reference example, as shown in FIGS. 14 and 15, a p-type channel having a region 31 having a different channel length at one end in the channel width direction (left and right direction in FIG. 14). Adjacent to the region 3, the n ⁺ type source region 4 and the n ⁺ type drain region 5 provided so as to sandwich the p type channel region 3, and the region 31 having different channel lengths of the p type channel region 3. And the p ⁺ type body contact region 9 provided as above, and the surplus carriers accumulated in the channel region 3 are taken out from the body contact region 9.

In the reference example 2, if the channel region 3 is formed so as to have a constant channel length, the source region 4 and the drain region 5 will be unavoidable due to an unavoidable deviation during manufacturing.
The body contact region 9 is connected to the junction between the channel region 3 and the channel region 3 to cause a short circuit. In order to avoid this short circuit, in the SOI type MOS semiconductor device of the second reference example, the channel region 3 has a region 31 having a different channel length at one end in the channel width direction.

Further, in the third reference example, as shown in FIG. 16, a p ⁻ type channel region 3 and an n ⁺ type source region 4 provided so as to sandwich the p ⁻ type channel region 3 and n ⁺ type drain region 5 and p ⁻ type channel region 3
And ap ⁻ type well region 91 provided so as to surround the n ⁺ type source region 4 and the n ⁺ type drain region 5, and part of the p ⁻ type well region 91 is used as a body contact. The region 92 is used to take out excess carriers accumulated in the channel region 3 from the body contact region 92 via the p ⁻ type well region 91.

In Reference Example 4, as shown in FIGS. 17 and 18, a p-type channel region 3 and a p-type channel region 3 are used.
N ⁺ -type source region 4 and n ⁺ -type drain region 5, p ⁺ -type body contact region 9, n ⁺ -type source region 4 and n ⁺ -type drain region 5 Has a p-type predetermined path 8 for electrically connecting the p-type channel region 3 and the p ⁺ -type body contact region 9 in the lower part of the p-type channel region 3, and the excess carriers accumulated in the channel region 3 are p-typed. It is taken out from the ⁺ type body contact region 9.

Of the drawings showing the cited examples, FIGS. 12, 14, 16 and 17 are in the same plane as the channel region 3, the source region 4 and the drain region 5 for simplification of description. However, in practice, for example, the gate insulating film 6 and the gate electrode 7 are formed above the channel region 3.
Needless to say, the contact wiring 11 is provided in the body contact regions 9 and 92.

[0026]

However, each of the above cited examples has various problems.

That is, in the reference example 1, since the body contact region 9 is arranged adjacent to the source / drain regions 4 and 5, the junction breakdown voltage between the body contact region 9 and the source / drain regions 4 and 5 is high. There was a problem that it decreased.

Further, since the n ⁺ type source region 4 and the drain region 5 are surrounded by the p type predetermined path 8, the capacitance becomes large and there is a problem that the speed cannot be increased.

Further, in the reference example 2, one MOS is used.
-Type semiconductor elements have channel regions 3 with different channel lengths.
Since 1 is provided, the following problem has occurred.

Regions 31 having different channel lengths are regions 71 having different gate lengths at the ends of the gate electrode 7 (see FIG. 15).
Are provided, and the regions 71 having different gate lengths of the gate electrode are used as a mask to perform ion implantation for forming the source and the drain, thereby forming in self-alignment. Therefore, a parasitic gate capacitance composed of a region 71 having a different gate length of the gate electrode and a region 31 having a different channel length is generated, which hinders speeding up.

The regions 31 having different channel lengths are provided in the channel region 3, as described above, because the body contact region 9 is connected to the junction between the source region 4 and the drain region 5 and the channel region 3. This is to prevent a short circuit due to this, so that the channel region 3 cannot have a constant channel length in the structure of the reference example 2. if,
If the channel region 3 is to have a constant channel length, it is connected to the channel region 3 of the body contact region 9 in order to ensure that the body contact region 9 is completely separated from the source region 4 and the drain region 5 during manufacturing. The length of the portion (vertical direction in FIG. 14) has to be made quite narrow, which is practically impossible.

Further, in the reference example 3, since the element region including the channel region 3, the source region 4 and the drain region 5 is surrounded by the well region 91, there is a problem that the capacitance is large and the speed cannot be increased. .

Further, since the body contact region 92 is a part of the well region 91 and the well region 91 is p ⁻ type (that is, the impurity concentration is low), there is a problem that the contact resistance is large.

In order to reduce the contact resistance,
If the impurity concentration of the well region 91 is increased, the junction breakdown voltage between the body contact region 92 and the source / drain regions 4, 5 will also be reduced.

Further, in the reference example 4, since the predetermined path 8 for electrically connecting the channel region 3 and the body contact region 9 is provided below the source region 4 and the drain region 5, the capacitance is large. There was a problem that speedup could not be measured.

In the above cited references 1 and 3, a body contact region of one conductivity type which constitutes a semiconductor device having an SOI structure is provided adjacent to a source region or drain region of another conductivity type, and a pn between both regions is provided. The junction is used to insulate the body contact region from the source / drain regions.

Therefore, these references do not point out any adverse effects caused by adjoining the body contact region to the source / drain regions, such as deterioration of electrical characteristics.

Further, in any of the cited examples 1 to 4, only the semiconductor device having the single SOI structure is described, and no consideration is given to the array in which a plurality of these single semiconductor devices are arranged.

For example, in the second reference example, since the body contact region 9 is arranged in the channel width direction of the channel region 3, there is a problem that a large restriction occurs in forming a gate array.

Therefore, the semiconductor devices in the reference examples 1 to 4 have a structure unsuitable for forming an array.

It is an object of the present invention to solve the above-mentioned various problems by the body contact region and the source / source region.
It is an object of the present invention to provide a MOS type semiconductor device having an SOI structure capable of preventing a decrease in breakdown voltage with respect to a drain region.

Another object of the present invention is to provide a semiconductor device having an SOI structure having a MOS type semiconductor element having an SOI structure capable of performing a speeded up operation by reducing parasitic capacitance as much as possible. It is in.

Still another object of the present invention is to provide the above SOI.
An object of the present invention is to provide a semiconductor gate array having an SOI structure in which a semiconductor device having a structure is formed into a gate array.

[0044]

In order to solve the above problems, the present invention provides a semiconductor device having an SOI structure and a semiconductor gate array having an SOI structure as follows.

That is, according to the present invention, there is provided an SOI structure semiconductor device including a MOS type semiconductor element formed on an insulator layer, wherein the MOS type semiconductor element is formed on the insulator layer. In a semiconductor device having an SOI structure, which has a channel region of a first conductivity type and two semiconductor regions of a second conductivity type formed on the insulator layer so as to sandwich the channel region, a body contact region; An SOI structure having a predetermined path for electrically connecting the channel region and the body contact region, and an insulating layer interposed between the body contact region and the semiconductor region. The semiconductor device can be obtained.

Further, according to the present invention, there is provided a semiconductor device having an SOI structure including a first insulating layer and a MOS type semiconductor element formed on the first insulating layer, wherein the MOS device is provided.
A channel region provided on the first insulator layer so that the type semiconductor element has a constant channel length in a predetermined direction and a constant channel width in a direction orthogonal to the predetermined direction; An SOI having a source region and a drain region provided on the first insulator layer so as to sandwich the channel region at both ends in the channel length direction.
In a semiconductor device having a structure, the semiconductor device is provided adjacent to at least one of the source region and the drain region, parallel to the channel width direction of the channel region, and
Second insulator layer formed on the insulator layer, a predetermined path provided so as to be connected to the channel region on the same plane as the source region and the drain region, and the source region and the drain An SOI structure having at least one of regions and a body contact region which is provided so as to sandwich the second insulator layer and which is electrically connected to the channel region through the predetermined path. The semiconductor device can be obtained.

According to the present invention, any one of the above S
In the semiconductor device of OI structure, the body contact region has a higher impurity concentration than that of the channel region, so that a semiconductor device of SOI structure is obtained.

According to the present invention, any one of the above S
In the semiconductor device having the OI structure, whether the predetermined path has substantially the same impurity concentration as that of the channel region,
Alternatively, it is possible to obtain a semiconductor device having an SOI structure, which has a higher impurity concentration than the channel region and a lower impurity concentration than the body contact region.

Furthermore, according to the present invention, the film thicknesses of the channel region, the source region, and the drain region are:
A semiconductor device having a thin film SOI structure, which is characterized by being formed in a range of 300 × 10 ⁻⁸ cm or more and 2000 × 10 ⁻⁸ cm or less, is obtained.

Further, according to the present invention, an SOI structure semiconductor gate array having a structure in which a plurality of the SOI structure semiconductor devices are arranged can be obtained.

Further, according to the present invention, in the semiconductor gate array of the SOI structure, a plurality of MOS type semiconductor elements share one body contact region, and the semiconductor gate array of the SOI structure is characterized. Is obtained.

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device having an SOI structure according to the present invention is a MOS type semiconductor device having an SOI structure provided with a body contact region for preventing a floating body effect, and has a constant channel length. Area and source /
Having a body contact region provided via a drain region and an insulator, and a predetermined path provided on the same plane as the source / drain region for electrically connecting the channel region and the body contact region. It is characterized by.

The SOI structure semiconductor gate array of the present invention is an array of a plurality of SOI structure semiconductor devices of the present invention, each of which has a SOI type MOS semiconductor element, and is formed into a gate array. One body contact region is shared by the MOS type semiconductor device of FIG.

The semiconductor device having the SOI structure and the semiconductor gate array having the SOI structure according to the present invention will be described below with reference to various embodiments.

In order to describe the present invention more specifically, the channel region is p-type.

(First Embodiment) A first embodiment of the present invention relates to a semiconductor device including a MOS type semiconductor element having an SOI structure, which is the basis of other embodiments described below. It is a thing.

The SOI structure semiconductor device according to the present embodiment has the structure shown in FIGS.

Specifically, the SO of the present embodiment will be described.
As shown in FIGS. 3 to 5, the semiconductor device having the I structure has a single crystal silicon substrate 1 and an SO on the single crystal silicon substrate 1.
A first insulator layer 2 formed by using the I technique, a p-type channel region 3 provided in a predetermined region on the first insulator layer 2, and one end of the channel region 3 The n ⁺ -type source region 4 provided on the first insulator layer 2 so as to be adjacent to it, and the first insulator layer 2 provided on the first insulator layer 2 so as to be adjacent to the other end of the channel region 3 n ⁺ type drain region 5
And a second semiconductor layer (gate insulating film) 6 formed on the channel region 3, and a gate electrode 7 formed on the gate insulating film 6.

Here, the left-right direction in FIGS. 1 and 2 is called the channel width direction, and the direction orthogonal to the channel width direction is called the channel length direction.

Therefore, as is apparent from FIG. 2, the channel region 3 has a constant channel length, and the source region 4 and the drain region 5 are adjacent to the channel region 3 in the channel length direction. To be understood.

In the illustrated semiconductor device having an SOI structure, the third insulator layer 10 is provided on the first insulator layer 2 so that the source region 4 is sandwiched between the channel region 3 and the source region 4.
And a body contact region 9 made of a p ^{+ +} type semiconductor region provided on the first insulator 2 layer so as to sandwich the third insulator layer 10 with the source region 4, and a first insulator layer. 2 on the channel region 3, the source region 4, and the drain region 5 along the channel length direction so as to electrically connect the channel region 3 and the body contact region 9. and a predetermined path 8 formed of a p ⁺ type semiconductor region.

Here, p ⁺ indicating the conductivity type of the predetermined region 8
The type means that it is p-type and has an impurity concentration higher than that of the channel region 3. The p ⁺⁺ type, which indicates the conductivity type of the body contact region 9, is p-type and has an impurity concentration higher than that of the predetermined region 8. Means high.

Further, practically, as shown in FIG. 3, in the body contact region 9, a contact wiring 11 for taking out excess carriers in the channel region 3 from the body contact region 9 to the outside of the element, The interlayer insulating film 13 provided so as to cover the entire element and the contact wiring 1
1 and a wiring layer 12 for body contact provided on the interlayer insulating film 13 so as to be electrically connected.

In the semiconductor device having the SOI structure having such a structure, the excess carriers accumulated in the channel region 3 pass through the predetermined path 8, the body contact region 9, the contact wiring 11, and the body contact wiring layer 12. It is pulled out to the outside.

Therefore, it is possible to prevent the so-called substrate floating effect in which the channel region electrically floats.

Further, in the SOI structure semiconductor device having such a structure, since the channel region 3 has a constant channel length, there is no increase in the gate capacitance which hinders the speedup.

Since the insulator layer 10 is provided between the body contact region 9 and the source region 4 except for the predetermined path 8, the junction breakdown voltage between the body contact region 9 and the source region 4 is lowered. Can be prevented.

Since the predetermined path 8 has a relatively low impurity concentration, and the predetermined path 8 is in contact with the source / drain regions 4 and 5 only at the ends in the channel width direction, the device The total capacity does not have to be large, and the speed can be increased.

Further, since the region corresponding to the well contact in the conventional bulk type gate array can be used as it is as the body contact, the design layout of the conventional bulk type gate array can be applied as it is.

Incidentally, in the first embodiment of the present invention,
The body contact region 9 is provided on the source region 4 side, but may be provided on the drain region 5 side.

Further, in the first embodiment of the present invention, the predetermined path 8 is provided both on the first insulator layer 2 and at the ends of the channel region 3 in the channel width direction. However, it suffices if the body contact region 9 and the channel region 3 are electrically connected to each other, for example, the first insulator layer 2
It may be provided on only one of the ends of the channel region 3 in the channel width direction above.

That is, it is sufficient that the predetermined path 8 is provided on the same surface as the source region 4 and the drain region 5 and that the body contact region 9 and the channel region 3 are electrically connected.

In the first embodiment of the present invention, the predetermined path 8 has a higher impurity concentration than the channel region 3 (p ⁺ type), and the body contact region 9 has a higher impurity concentration than the predetermined path. Although it is assumed to be (p ⁺⁺ type), the predetermined path 8 may have an impurity concentration (p type) substantially the same as that of the channel region 3, as shown in FIG. 6, for example.

Further, in the first embodiment of the present invention, the film thickness of the single crystal silicon layer forming the channel region 3, the source region 4 and the drain region 5 is not specified, but it is 300 × 10 5. ^-8 cm or more 2000 x 10 ^-8 cm
A thin film SOI structure having a film thickness formed in the following range may be used.

The thin film SOI structure has an advantage that the punch through phenomenon can be further prevented as described above.

(Second Embodiment) A semiconductor gate array having an SOI structure according to a second embodiment of the present invention is applied with the feature of the shape of the semiconductor device having the SOI structure according to the first embodiment. This is an array in which four MOS type semiconductor devices having an SOI structure share one body contact region.

In other words, the SOI structure semiconductor gate array according to the second embodiment of the present invention, as shown in FIGS. 7 and 8, is a unit cell having four SOI structure MOS type semiconductor devices. Are arranged in a plurality.

Here, the unit cell of the second embodiment is
S is formed on the single crystal silicon substrate 1 and the single crystal silicon substrate 2.
A first insulator layer 2 formed using the OI technique;
And the first and second semiconductor elements which are formed on the insulator layer 2 and share the drain region 5 with each other, and the first and second semiconductor elements which are formed on the first insulator layer 2 and share the drain region 5 with each other. Third and fourth semiconductor elements, and a fourth insulator layer 1 sequentially formed between the second semiconductor element and the third semiconductor element
0, body contact region 9, and fifth insulator layer 10
And the channel region 3 of each of the first to fourth semiconductor elements.
A predetermined path 8 provided on the first insulator layer 2 so as to electrically connect the first contact layer 9 and the body contact region 9;
And the field oxide film 14 provided so as to surround all of them.

Specifically, each M of this embodiment will be described.
The OS-type semiconductor element includes a p-type channel region 3 provided in a predetermined region on the first insulator layer 2 and a channel region 3.
N ⁺ -type source region 4 provided on the first insulator layer 2 so as to be adjacent to one end of the first insulator layer, and the first insulator layer 4 so as to be adjacent to the other end of the channel region 3. N ⁺ -type drain region 5 provided on the second region, a second insulator layer (gate insulating film) 6 formed on the channel region 3, and a gate electrode 7 formed on the gate insulating film 6. have.

Here, the left-right direction in FIG. 7 is called the channel width direction, and the direction orthogonal to the channel width direction is called the channel length direction.

Therefore, as is clear from FIG. 7, each channel region 3 has a constant channel length, and each source region 4 and drain region 5 are adjacent to the channel region 3 in the channel length direction. It is understood that

From the above, the unit cell of the present embodiment, more specifically, the third insulating layer (field oxide film) 14 provided on the first insulating layer 2 and the third insulating layer A first MOS type semiconductor element in which the body layer and the channel region 3 are arranged so as to sandwich the source region 4, and a second MOS type semiconductor element in which the drain region 5 is shared with the first MOS type semiconductor element.
Of the second MOS type semiconductor element and the source region 4 of the second MOS type semiconductor element are sandwiched between the channel region 3 of the second MOS type semiconductor element and a fourth insulating layer provided on the first insulator layer 2. A body made of a p ^{+ +} type semiconductor region provided on the first insulator layer 2 such that the body layer 10 and the fourth insulator layer 10 are sandwiched between the source region 4 of the second MOS type semiconductor element. And a contact region 9.

The unit cell of the present embodiment has the following structure on the side opposite to the first and second MOS type semiconductor elements when viewed from the body contact region 9.

That is, the unit cell of the present embodiment further includes
The fifth insulator layer 10 provided on the first insulator layer 2 so as to sandwich the body contact region 9 with the fourth insulator layer 10, the fifth insulator layer 10 and the channel region 3 A third MOS type semiconductor element arranged so as to sandwich the source region 4, a fourth MOS type semiconductor element arranged so as to share the drain region 5 with the third MOS type semiconductor element, and a fourth MOS type semiconductor element The source region 4 of the MOS type semiconductor device is
And a sixth insulator layer (field oxide film) 14 provided on the first insulator layer 2 so as to be sandwiched between the first insulator layer 2 and the channel region 3 of the MOS semiconductor element.

In addition, the unit cell of the present embodiment is such that all the first to fourth MOSs are on the first insulator layer 2.
Formed at the end of the channel type semiconductor element in the channel width direction along the channel length direction to electrically connect the channel region 3 and the body contact region 9 of each of the first to fourth MOS type semiconductor elements. ^A predetermined path 8 formed of a ⁺ type semiconductor region, first to fourth MOS type semiconductor elements, a fourth insulator layer 10, a body contact region 9 and a fifth
The insulating layer 10 and the predetermined path 8 of the first to fourth MO layers.
The seventh insulating layer (field oxide film) 14 is provided so as to be sandwiched between the ends of the S-type semiconductor element in the channel width direction.

Here, p ⁺ indicating the conductivity type of the predetermined region 8
The type means that it is p-type and has an impurity concentration higher than that of the channel region 3. The p ⁺⁺ type, which indicates the conductivity type of the body contact region 9, is p-type and has an impurity concentration higher than that of the predetermined region 8. Means high.

Further, the SOI structure semiconductor gate array of the present embodiment has a structure in which a plurality of unit cells are arranged, and each adjacent unit cell has a field oxide film (the third unit cell) surrounding the peripheral portion. Insulator layer, sixth insulator layer, seventh
Any one of the above (insulator layers 14) is shared.

Here, in FIG. 7, for simplification of the drawing, the unit cells are arranged only in the channel length direction, but it is also said that they are similarly arranged in the channel width direction. There is no end. Also, in FIG. 8, only one layer is shown for simplification of the drawing, but it goes without saying that a multilayer may be used.

Incidentally, also in the semiconductor gate array of the SOI structure of the present embodiment, as shown in FIG. 8, practically, in each body contact region 9, the body contact region 9 to the channel region 3 are formed. Contact wirings 11 for taking out excess carriers from the device to the outside of the device, and an interlayer insulating film 13 provided so as to cover the entire plurality of semiconductor devices.
And a body contact wiring layer 12 provided on the interlayer insulating film 13 so as to be electrically connected to each contact wiring 11.

In the semiconductor gate array of the SOI structure having such a structure, the excess carriers accumulated in the channel region 3 of each semiconductor element are provided with a predetermined path 8, body contact region 9, contact wiring 11, body contact. It is pulled out to the outside through the wiring layer 12.

Therefore, it is possible to prevent the so-called substrate floating effect in which the channel region electrically floats.

Also in the semiconductor gate array having the SOI structure having the above-described structure, the channel region 3 has a constant channel length as in the first embodiment, and therefore the speedup is hindered. There is no increase in the gate capacitance.

Since the insulator layer 10 is provided between each body contact region 9 and the source region 4 closest to each body region except for the predetermined path 8, the body contact region 9 and the source region 4 are separated from each other. It is possible to prevent the junction breakdown voltage from decreasing.

Since the predetermined path 8 has a relatively low impurity concentration, and the predetermined path 8 is in contact with the source / drain regions 4 and 5 only at the ends in the channel width direction, The capacity of each semiconductor element does not need to be large, and the speed of the entire semiconductor gate array can be increased.

Further, in the semiconductor gate array of the SOI structure of the second embodiment, since four semiconductor elements share one body contact region 9, miniaturization is achieved in the gate array as a whole. ing.

In the second embodiment of the present invention as well, as in the first embodiment, the body contact region 9 is provided on the source region 4 side, but is provided on the drain region 5 side. You may be taken.

Further, in the second embodiment of the present invention, the predetermined path 8 is provided both on the first insulator layer 2 and at the end of the channel region 3 in the channel width direction. However, it suffices if the body contact region 9 and the channel region 3 are electrically connected to each other. For example, the body contact region 9 and the channel region 3 are provided on only one end of the channel region 3 in the channel width direction on the first insulator layer 2. It may be.

That is, it is sufficient that the predetermined path 8 is provided on the same surface as the source region 4 and the drain region 5 and that the body contact region 9 and the channel region 3 are electrically connected.

In the second embodiment of the present invention, the predetermined path 8 has a higher impurity concentration than the channel region 3 (p ⁺ type), and the body contact region 9 has a higher impurity concentration than the predetermined path 8. Although it is assumed to be high (p ⁺⁺ type), the predetermined path 8 may have substantially the same impurity concentration (p type) as the channel region.

Further, in the second embodiment of the present invention, although the film thickness of the single crystal silicon layer forming the channel region 3, the source region 4 and the drain region 5 is not particularly specified, it is 300 × 10. ^-8 cm or more 2000 x 10 ^-8 cm
A thin film SOI structure having a film thickness formed in the following range may be used.

The thin film SOI structure has an advantage that the punch through phenomenon or the like can be prevented as described above.

(Third Embodiment) A semiconductor gate array having an SOI structure according to a third embodiment of the present invention is applied with the feature of the shape of the semiconductor device having the SOI structure according to the first embodiment. Two MOS type semiconductor devices having an SOI structure are arrayed so as to share one body contact region.

In other words, the semiconductor gate array having the SOI structure according to the third embodiment of the present invention is the same as that shown in FIGS.
As shown in (1), a plurality of unit cells having two MOS structure semiconductor elements having an SOI structure are arranged.

Here, the unit cell of the third embodiment is
S is formed on the single crystal silicon substrate 1 and the single crystal silicon substrate 2.
A first insulator layer 2 formed using the OI technique;
A first semiconductor element formed on the insulator layer, a third insulator layer 10, a body contact region 9, a fourth insulator layer 10, a second semiconductor element, and A predetermined path 8 provided on the first insulating layer 2 so as to electrically connect the channel region 3 and the body contact region 9 of each of the second semiconductor elements, and all of them in the channel width direction ( It has a field oxide film (not shown) provided on the first insulator layer 2 so as to sandwich it in the left-right direction in FIG.

More specifically, each M of the present embodiment will be described.
The OS-type semiconductor element includes a p-type channel region 3 provided in a predetermined region on the first insulator layer 2 and a channel region 3.
N ⁺ -type source region 4 provided on the first insulator layer 2 so as to be adjacent to one end of the first insulator layer, and the first insulator layer 4 so as to be adjacent to the other end of the channel region 3. The n + -type drain region 5 provided on the second region, the second insulator layer (gate insulating film) 6 formed on the channel region 3, and the gate electrode 7 formed on the gate insulating film 6. Have

The left-right direction of FIG. 9 is called the channel width direction, and the direction orthogonal to the channel width direction is called the channel length direction.

Therefore, as is apparent from FIG. 9, each channel region 3 has a constant channel length, and each source region 4 and drain region 5 are adjacent to the channel region 3 in the channel length direction. It is understood that

From the above, the unit cell of the present embodiment, more specifically, the first MOS type semiconductor device and the first MO type semiconductor device.
A third layer provided on the first insulator layer 2 so as to be adjacent to the source region 4 of the S-type semiconductor element in the channel width direction.
Of the insulating layer 10 and the third insulating layer 10 of the first MOS
P ⁺ -type body contact region 9 provided on the first insulator layer 2 so as to be sandwiched between the first semiconductor layer and the third type semiconductor element, and the third contact layer 9 is sandwiched between the body contact region 9 and the first insulator layer 10. Fourth insulator layer 1 provided on body layer 2
0, and the second MOS type semiconductor element in which the fourth insulator layer 10 and the channel region 3 are arranged so as to sandwich the source region 4.

Further, the unit cell of the present embodiment is arranged on the first insulator layer 2 along the channel length direction at the end portions in the channel width direction of all the first and second MOS type semiconductor elements. And has a p ⁺ type predetermined path 8 for electrically connecting the channel region 3 and the body contact region 9 of the first and second MOS type semiconductor elements.

Here, p ⁺ indicating the conductivity type of the predetermined region 8
The type means that it is p-type and has an impurity concentration higher than that of the channel region 3. The p ⁺⁺ type, which indicates the conductivity type of the body contact region 9, is p-type and has an impurity concentration higher than that of the predetermined region 8. Means high.

Further, in the unit cell of this embodiment, the first and second MOS type semiconductor elements, the third and fourth insulator layers 10, the body contact region 9 and the predetermined path 8 are formed in the channel width direction. And a fifth insulator layer (field oxide film) 14 (not shown) provided so as to be sandwiched at the end of the.

The SOI structure semiconductor gate array according to the present embodiment has a structure in which a plurality of unit cells are arranged, and each adjacent unit cell has a fifth insulator in the channel width direction. The layer 14 shares the drain region 5 in the channel length direction.

Here, in FIG. 9, for simplification of the drawing, the unit cells are shown arranged only in the channel length direction, but it goes without saying that they are also arranged in the channel width direction in the same manner. Yes. Also in FIG.
For the sake of simplification of the drawing, only the form of cleaning is shown, but it goes without saying that a multilayer structure may be used.

In the SOI structure semiconductor gate array of the present embodiment, as shown in FIG. 10, the body contact regions 9 to the channel regions 3 are practically used as shown in FIG. Contact wirings 11 for taking out excess carriers from the device to the outside of the device, and the interlayer insulating film 1 provided so as to cover the entire plurality of semiconductor devices.
3 and each body contact wiring layer 12 provided on the interlayer insulating film 13 so as to be electrically connected to each contact wiring 11.

In the semiconductor gate array of the SOI structure having such a structure, the excess carriers accumulated in the channel region 3 of each semiconductor element have a predetermined path 8, a body contact region 9, a contact wiring 11 and a body contact. It is pulled out to the outside through the wiring layer 12.

Therefore, it is possible to prevent the so-called substrate floating effect in which the channel region 3 is electrically floated.

Further, also in the semiconductor gate array of the SOI structure having the above-mentioned structure, the channel region 3 has a constant channel length as in the first embodiment, and therefore the speedup is hindered. There is no increase in the gate capacitance.

Since the insulator layer 10 is provided between each body contact region 9 and the source region 4 closest to each body region except for the predetermined path 8, the body contact region 9 and the source region 4 are separated from each other. It is possible to prevent the junction breakdown voltage from decreasing.

Since the predetermined path 8 has a relatively low impurity concentration, and the predetermined path 8 is in contact with the source / drain regions 4 and 5 only at the ends in the channel width direction, The capacity of each semiconductor element does not need to be large, and the speed of the entire semiconductor gate array can be increased.

Further, in the semiconductor gate array of the SOI structure of the third embodiment, since two semiconductor elements share one body contact region 9, miniaturization is achieved in the gate array as a whole. ing.

In the third embodiment of the present invention as well, as in the first embodiment, the body contact region 9 is provided on the source region 4 side, but is provided on the drain region 5 side. You may be taken.

In addition, in the third embodiment of the present invention, the predetermined path 8 is provided on both the ends of the channel region 3 in the channel width direction on the first insulator layer 2. However, it suffices if the body contact region 9 and the channel region 3 are electrically connected to each other. For example, the body contact region 9 and the channel region 3 are provided on only one end of the channel region 3 in the channel width direction on the first insulator layer 2. It may be.

That is, it is sufficient that the predetermined path 8 is provided on the same surface as the source region 4 and the drain region 5 and that the body contact region 9 and the channel region 3 are electrically connected.

In the third embodiment of the present invention, the predetermined path 8 has a higher impurity concentration than the channel region 3 (p ⁺ type), and the body contact region 9 has a higher impurity concentration than the predetermined path 8. Although it is assumed to be high (p ⁺⁺ type), the predetermined path 8 may have substantially the same impurity concentration (p type) as the channel region.

Further, in the third embodiment of the present invention, although the film thickness of the single crystal silicon layer forming the channel region 3, the source region 4 and the drain region 5 is not particularly specified, it is 300 × 10. ^-8 cm or more 2000 x 10 ^-8 cm
A thin film SOI structure having a film thickness formed in the following range may be used.

The thin film SOI structure has an advantage that the punch through phenomenon or the like can be prevented as described above.

[0127]

As described above, according to the present invention, the floating body effect can be prevented by having the body contact region for taking out excess carriers accumulated in the channel region. .

Further, according to the present invention, since the insulator layer is interposed between the body contact region and the source and drain regions, the junction breakdown voltage between the body contact region and the source and drain regions is lowered. Prevented SO
A MOS type semiconductor device having an I structure can be obtained.

Further, according to the present invention, since the channel length is constant within one MOS type semiconductor device, there is no increase in gate capacitance which hinders speeding up.

Further, according to the present invention, the predetermined path for electrically connecting the body contact region and the channel region has a relatively low impurity concentration, and the predetermined path is the source / drain region. Since the area in contact with S is relatively small, the capacity has been minimized and the speed has been increased.
A MOS type semiconductor device having an OI structure can be obtained.

Further, according to the present invention, it is possible to obtain an SOI structure MOS type semiconductor gate array in which the above SOI structure MOS type semiconductor device is formed into a gate array.

Further, according to the present invention, it is possible to obtain a MOS type semiconductor device having an SOI structure in which miniaturization is achieved by sharing the body contact region with a plurality of MOS type semiconductor elements having an SOI structure.

[Brief description of drawings]

FIG. 1 is a top view of a semiconductor device having an SOI structure according to a first embodiment of the present invention in which an interlayer insulating film and a field oxide film are omitted.

FIG. 2 is a diagram showing a configuration on the same plane as a source / drain region in a semiconductor device having an SOI structure according to a first embodiment of the present invention.

3 is a diagram showing a cross section taken along line 3-3 in FIG.

4 is a diagram showing a cross section taken along line 4-4 in FIG.

5 is a view showing a cross section taken along line 5-5 in FIG.

FIG. 6 is a diagram showing another example of the semiconductor device having the SOI structure according to the first embodiment of the present invention.

FIG. 7 is a top view of an SOI structure semiconductor gate array according to a second embodiment of the present invention in which an interlayer insulating film and a field oxide film are omitted.

8 is a view showing a cross section taken along line 8-8 of FIG. 7, and is a view in which an interlayer insulating film and a field oxide film are added.

FIG. 9 is a top view of an SOI structure semiconductor gate array according to a third embodiment of the present invention in which an interlayer insulating film and a field oxide film are omitted.

10 is a view showing a cross section taken along line 10-10 of FIG. 9, and is a view in which an interlayer insulating film and a field oxide film are added.

FIG. 11 is a schematic cross-sectional view of a conventional semiconductor device having a general SOI structure.

FIG. 12 is a view showing the same plane as the source / drain regions of the SOI structure semiconductor device of the first reference example;

13 is a sectional view taken along line 13-13 in FIG. 12, showing a field oxide film added.

FIG. 14 is a view showing the same plane as the source / drain regions of the semiconductor device having the SOI structure of Cited Example 2;

15 is a diagram showing that a gate electrode is provided on the channel region in FIG.

16 is a view showing the same plane as the source / drain regions of the semiconductor device having the SOI structure of Cited Example 3. FIG.

FIG. 17 is a view showing the same plane as the source / drain regions of the semiconductor device having the SOI structure of Cited Example 4;

FIG. 18 shows a semiconductor device having an SOI structure of Cited Example 4 in FIG.
It is a figure which shows the cross section when it cut | disconnects at the position of 18-18.

[Explanation of symbols]

 1 Single Crystal Silicon Substrate 2 First Insulator Layer 3 Channel Region 4 Source Region 5 Drain Region 6 Gate Insulating Film 7 Gate Electrode 8 Predetermined Path 9 Body Contact Region 10 Insulator Layer 11 Contact Wiring 12 Body Contact Wiring Layer 13 Interlayer insulating film 14 Field insulating film 31 Region with different channel length 71 Region with different gate length 91 Well region 92 Body contact region

Claims (18)

[Claims] 1. A semiconductor device having an SOI structure including a MOS type semiconductor element formed on an insulator layer, wherein the MOS type semiconductor element is a channel of a first conductivity type formed on the insulator layer. A semiconductor device having an SOI structure having a region and two second-conductivity-type semiconductor regions formed on the insulator layer so as to sandwich the channel region, a body contact region, the channel region, and the body contact A semiconductor device having an SOI structure, comprising a predetermined path electrically connecting to a region, and an insulating layer interposed between the body contact region and the semiconductor region. 2. A semiconductor device having an SOI structure including a first insulating layer and a MOS type semiconductor element formed on the first insulating layer, wherein the MOS type semiconductor element is arranged in a predetermined direction. A channel region provided on the first insulator layer so as to have a constant channel length and a constant channel width in a direction orthogonal to the predetermined direction, and the channel region in the channel length direction. The first so that both ends are clamped
A semiconductor device having an SOI structure having a source region and a drain region provided on the insulating layer of the above, the semiconductor device being provided adjacent to at least one of the source region and the drain region and being parallel to the channel width direction of the channel region. And a second insulating layer formed on the first insulating layer and on the same surface as the source region and the drain region so as to be connected to the channel region. A predetermined path that extends in the direction, and is provided so as to sandwich the second insulator layer with at least one of the source region and the drain region, and is electrically connected to the channel region through the predetermined path. An SOI structure semiconductor device having a body contact region. 3. A first insulator layer and a first insulator layer having a constant channel length in a predetermined direction and a constant channel width in a direction orthogonal to the predetermined direction. A first conductivity type channel region provided in a predetermined region above, and a second region provided on the first insulator layer so as to be adjacent to one end of the channel region in the channel length direction. A first semiconductor region of conductivity type and a second semiconductor region of second conductivity type provided on the first insulator layer so as to be adjacent to the other end of the channel region in the channel length direction. In a semiconductor device having an SOI structure including a MOS type semiconductor element having an SOI structure, the semiconductor device having a second insulator layer formed on the channel region and an electrode formed on the second insulator layer. , Parallel to the channel width direction And a third insulator layer provided on the first insulator layer so as to be adjacent to the first semiconductor region, and the third insulator layer with the first semiconductor region. And a third semiconductor region of the first conductivity type provided on the first insulator layer so as to be sandwiched between and along at least one end of the channel region in the channel width direction in the channel length direction. A fourth of a first conductivity type provided on the first insulator layer;
And a fourth semiconductor region electrically connecting the third semiconductor region and the channel region, wherein the third semiconductor region is higher in impurities than the channel region. A semiconductor device having an SOI structure, which has a high concentration. 4. The semiconductor device having an SOI structure according to claim 3, wherein the third semiconductor region is a body contact region, a contact wiring is provided at a predetermined position on the third semiconductor region, and the channel is formed. The surplus carriers accumulated in the area are added to the fourth
Through the semiconductor region and the body contact region of
SO characterized by being taken out from the contact wiring
A semiconductor device having an I structure. 5. The SOI structure semiconductor device according to claim 3, wherein the fourth semiconductor region has substantially the same impurity concentration as that of the channel region. Semiconductor device. 6. The semiconductor device having an SOI structure according to claim 3, wherein the fourth semiconductor region has an impurity concentration higher than that of the channel region and an impurity concentration higher than that of the third semiconductor region. A semiconductor device having an SOI structure characterized by low 7. The semiconductor device having the SOI structure according to claim 3, wherein the film thickness of each of the channel region, the first semiconductor region, and the second semiconductor region. Is a semiconductor device having a thin film SOI structure, which is formed in a range of 300 × 10 ⁻⁸ cm or more and 2000 × 10 ⁻⁸ cm or less. 8. A semiconductor gate array in which a plurality of MOS type semiconductor elements are arranged, wherein each MOS type semiconductor element has a common channel region, source region and drain region of the MOS type semiconductor element. A semiconductor gate array having an SOI structure, which is provided on the insulator layer so as to be in contact with the layer. 9. A MOS type semiconductor device having an SOI structure formed on a first insulator layer is arranged in plural, and the MOS type semiconductor devices adjacent to each other on the first insulator layer are separated from each other. In the semiconductor gate array of the SOI structure having a second insulator layer for achieving the above, each MOS type semiconductor element has a constant channel length in a predetermined direction and a constant direction in a direction orthogonal to the predetermined direction. And a channel region provided on the first insulator layer so as to have a channel width of, and both end portions of the channel region in the channel length direction are sandwiched between the first insulator layer. In a semiconductor gate array of SOI structure having a source region and a drain region, at least one end of the channel region of each MOS semiconductor element in the channel width direction. And a body contact region electrically connected to the channel region of each of the MOS type semiconductor devices via the predetermined route formed along the channel length direction in the channel region. A third body for separating the body contact region for pulling out excess carriers accumulated in the body contact region, and the body contact region and each of the MOS type semiconductor elements adjacent to the body contact region except for the predetermined path. A semiconductor gate array having an SOI structure, comprising an insulator layer, and the plurality of MOS semiconductor elements share the body contact region. 10. A first insulator layer on the first insulator layer so as to have a constant channel length in a predetermined direction and a constant channel width in a direction orthogonal to the predetermined direction. A first conductivity type channel region provided in a predetermined region, and a second conductivity type provided on the first insulator layer so as to be adjacent to one end of the channel region in the channel length direction. A first semiconductor region, and a second conductivity type second semiconductor region provided on the first insulator layer so as to be adjacent to the other end of the channel region in the channel length direction. A semiconductor of SOI structure in which a plurality of MOS type semiconductor elements of SOI structure having a second insulator layer formed on the channel region and an electrode formed on the second insulator layer are arranged. A gate array, wherein A third insulator layer provided on the body layer,
A first MOS type semiconductor element in which the third insulator layer and the channel region are arranged so as to sandwich the first semiconductor region, the first MOS type semiconductor element and the second semiconductor The second MO arranged to share a region
The S-type semiconductor element and the first semiconductor region of the second MOS-type semiconductor element are provided on the first insulator layer so as to be sandwiched between the S-type semiconductor element and the channel region of the second MOS-type semiconductor element. A first conductive layer provided on the first insulating layer such that the fourth insulating layer is sandwiched between the fourth insulating layer and the first semiconductor region of the second MOS semiconductor element. A third semiconductor region of a mold, a fifth insulator layer provided on the first insulator layer so as to sandwich the third semiconductor region with the fourth insulator layer, and the fifth insulator layer. A third MOS type semiconductor element in which the insulating layer and the channel region are arranged so as to sandwich the first semiconductor region, and the third MOS type semiconductor element and the second semiconductor region are shared. And a fourth MOS semiconductor device arranged so as to A sixth insulator layer provided on the first insulator layer so as to sandwich the first semiconductor region of the MOS semiconductor device with the channel region of the fourth MOS semiconductor device; 1st to 4th MOS
Of the first to fourth MOS type semiconductor elements formed on the first insulator layer so as to extend along at least one end of the channel region of the channel type semiconductor element in the channel width direction in the channel length direction. A fourth semiconductor region of a first conductivity type that electrically connects the channel region and the third semiconductor region, the first to fourth MOS semiconductor devices, the fourth insulator layer, and the fourth insulator layer. A plurality of unit cells having a third semiconductor region, a fifth insulator layer, and a seventh insulator layer provided so as to sandwich the fourth semiconductor region at an end portion in the channel width direction are arranged. The impurity concentration of each of the third semiconductor regions of the plurality of unit cells is set higher than that of the channel regions of the first to fourth MOS semiconductor devices, and the adjacent unit cells are The above The semiconductor gate array SOI structure, wherein a third insulator layer and the sixth insulating layer share any one of said seventh dielectric layer. 11. The SOI structure semiconductor gate array according to claim 10, wherein the third semiconductor region is a body contact region, and a contact wiring is provided at a predetermined position on the third semiconductor region, Surplus carriers accumulated in the channel regions of the first to fourth MOS semiconductor devices are extracted from the contact wiring via the fourth semiconductor region and the body contact region, and have a SOI structure. Gate array. 12. The S according to claim 10 or 11.
In the semiconductor gate array having an OI structure, the fourth semiconductor region has the same impurity concentration as that of the channel regions of the first to fourth MOS semiconductor devices, and the semiconductor gate array has an SOI structure. 13. The S according to claim 10 or 11.
In the semiconductor gate array having an OI structure, the fourth semiconductor region has a higher impurity concentration than the channel regions of the first to fourth MOS semiconductor devices,
An SOI structure semiconductor gate array having an impurity concentration lower than that of the third semiconductor region. 14. A first insulator layer on the first insulator layer having a constant channel length in a predetermined direction and a constant channel width in a direction orthogonal to the predetermined direction. A first conductivity type channel region provided in a predetermined region, and a second conductivity type provided on the first insulator layer so as to be adjacent to one end of the channel region in the channel length direction. A first semiconductor region, and a second conductivity type second semiconductor region provided on the first insulator layer so as to be adjacent to the other end of the channel region in the channel length direction. A semiconductor of SOI structure in which a plurality of MOS type semiconductor elements of SOI structure having a second insulator layer formed on the channel region and an electrode formed on the second insulator layer are arranged. A gate array, wherein the first M An S-type semiconductor element and the first semiconductor region of the first MOS-type semiconductor element sandwiched between the channel region of the first MOS-type semiconductor element and provided on the first insulator layer. A third insulator layer and the third
A third semiconductor region of the first conductivity type provided on the first insulator layer so as to sandwich the second insulator layer between the third semiconductor region and the first MOS type semiconductor element. Three
A fourth insulator layer provided on the first insulator layer so as to sandwich the first semiconductor region, and the fourth insulator layer and the channel region sandwich the first semiconductor region. The second MOS type semiconductor element disposed in the first and second MOS type semiconductor elements and at least one end in the channel width direction of the channel regions of the first and second MOS type semiconductor elements so as to extend along the channel length direction. A fourth semiconductor region of a first conductivity type, which is formed on a first insulator layer and electrically connects the channel region and the third semiconductor region of the first and second MOS type semiconductor devices, The first and second
Of the MOS type semiconductor device, the third and fourth insulator layers, the third semiconductor region and the fourth semiconductor region are sandwiched at the ends in the channel width direction. A plurality of unit cells having an insulator layer are arranged, and the impurity concentration of each of the third semiconductor regions of the plurality of unit cells is higher than that of the channel regions of the first and second MOS semiconductor devices. The adjacent unit cells include the second semiconductor region of the first MOS type semiconductor device, the second semiconductor region of the second MOS type semiconductor device, and the fifth insulator layer. And a semiconductor gate array of SOI structure. 15. The semiconductor gate array of SOI structure according to claim 14, wherein the third semiconductor region is a body contact region, and a contact wiring is provided at a predetermined position on the third semiconductor region, Surplus carriers accumulated in the channel regions of the first and second MOS semiconductor devices are extracted from the contact wiring via the fourth semiconductor region and the body contact region, and have a SOI structure. Gate array. 16. The S according to claim 14 or 15.
In the semiconductor gate array of OI structure, the fourth semiconductor region has the same impurity concentration as that of the channel regions of the first and second MOS type semiconductor devices, and the semiconductor gate array of SOI structure. 17. The S according to claim 14 or claim 15.
In the semiconductor gate array having an OI structure, the fourth semiconductor region has a higher impurity concentration than the channel regions of the first and second MOS semiconductor devices,
An SOI structure semiconductor gate array having an impurity concentration lower than that of the third semiconductor region. 18. The semiconductor gate array having an SOI structure according to claim 10, wherein the MOS semiconductor element is the channel region, the first semiconductor region, and the second semiconductor. A semiconductor gate array having an SOI structure, which is a MOS type semiconductor device having a thin film SOI structure formed in a region having a thickness of 300 × 10 ⁻⁸ cm or more and 2000 × 10 ⁻⁸ cm or less.