JP2003243576A5 - - Google Patents
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- Publication number
- JP2003243576A5 JP2003243576A5 JP2002036466A JP2002036466A JP2003243576A5 JP 2003243576 A5 JP2003243576 A5 JP 2003243576A5 JP 2002036466 A JP2002036466 A JP 2002036466A JP 2002036466 A JP2002036466 A JP 2002036466A JP 2003243576 A5 JP2003243576 A5 JP 2003243576A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- electrode
- semiconductor
- semiconductor device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002036466A JP3741274B2 (ja) | 2002-02-14 | 2002-02-14 | 半導体装置 |
| US10/366,347 US6661101B2 (en) | 2002-02-14 | 2003-02-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002036466A JP3741274B2 (ja) | 2002-02-14 | 2002-02-14 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003243576A JP2003243576A (ja) | 2003-08-29 |
| JP2003243576A5 true JP2003243576A5 (https=) | 2005-07-07 |
| JP3741274B2 JP3741274B2 (ja) | 2006-02-01 |
Family
ID=27655039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002036466A Expired - Lifetime JP3741274B2 (ja) | 2002-02-14 | 2002-02-14 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6661101B2 (https=) |
| JP (1) | JP3741274B2 (https=) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6847123B2 (en) * | 2002-04-02 | 2005-01-25 | Lsi Logic Corporation | Vertically staggered bondpad array |
| US7303113B2 (en) * | 2003-11-28 | 2007-12-04 | International Business Machines Corporation | Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers |
| US20060175712A1 (en) * | 2005-02-10 | 2006-08-10 | Microbonds, Inc. | High performance IC package and method |
| US20070145607A1 (en) * | 2005-12-28 | 2007-06-28 | Mathew Ranjan J | System to wirebond power signals to flip-chip core |
| US7638863B2 (en) * | 2006-08-31 | 2009-12-29 | Semiconductor Components Industries, Llc | Semiconductor package and method therefor |
| WO2008132814A1 (ja) * | 2007-04-18 | 2008-11-06 | Panasonic Corporation | 部品内蔵基板と、これを用いた電子モジュール及び電子機器 |
| US7825527B2 (en) * | 2008-06-13 | 2010-11-02 | Altera Corporation | Return loss techniques in wirebond packages for high-speed data communications |
| US9515032B1 (en) | 2015-08-13 | 2016-12-06 | Win Semiconductors Corp. | High-frequency package |
| US11152326B2 (en) | 2018-10-30 | 2021-10-19 | Stmicroelectronics, Inc. | Semiconductor die with multiple contact pads electrically coupled to a lead of a lead frame |
| US10978419B1 (en) * | 2019-10-14 | 2021-04-13 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3472455B2 (ja) * | 1997-09-12 | 2003-12-02 | 沖電気工業株式会社 | 半導体集積回路装置及びそのパッケージ構造 |
-
2002
- 2002-02-14 JP JP2002036466A patent/JP3741274B2/ja not_active Expired - Lifetime
-
2003
- 2003-02-14 US US10/366,347 patent/US6661101B2/en not_active Expired - Lifetime
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