JP2003228982A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JP2003228982A
JP2003228982A JP2002020721A JP2002020721A JP2003228982A JP 2003228982 A JP2003228982 A JP 2003228982A JP 2002020721 A JP2002020721 A JP 2002020721A JP 2002020721 A JP2002020721 A JP 2002020721A JP 2003228982 A JP2003228982 A JP 2003228982A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
semiconductor integrated
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002020721A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003228982A5 (enExample
Inventor
Shigeru Nakahara
茂 中原
Masayuki Iwahashi
誠之 岩橋
Takeshi Suzuki
武史 鈴木
Keiichi Higeta
恵一 日下田
Kazuo Kanetani
一男 金谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2002020721A priority Critical patent/JP2003228982A/ja
Priority to US10/345,186 priority patent/US6826109B2/en
Publication of JP2003228982A publication Critical patent/JP2003228982A/ja
Publication of JP2003228982A5 publication Critical patent/JP2003228982A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2002020721A 2002-01-29 2002-01-29 半導体集積回路装置 Pending JP2003228982A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002020721A JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置
US10/345,186 US6826109B2 (en) 2002-01-29 2003-01-16 Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002020721A JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2003228982A true JP2003228982A (ja) 2003-08-15
JP2003228982A5 JP2003228982A5 (enExample) 2005-08-18

Family

ID=27606291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002020721A Pending JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置

Country Status (2)

Country Link
US (1) US6826109B2 (enExample)
JP (1) JP2003228982A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3948933B2 (ja) * 2001-11-07 2007-07-25 富士通株式会社 半導体記憶装置、及びその制御方法
US7443737B2 (en) 2004-03-11 2008-10-28 International Business Machines Corporation Register file
US20080168257A1 (en) * 2007-01-05 2008-07-10 Glenn Lawrence Marks Interface assembly for coupling a host to multiple storage devices
US20140184288A1 (en) * 2012-12-27 2014-07-03 Samsung Electronics Co., Ltd. Semiconductor circuit and method for operating the same
EP3515959A1 (en) 2016-09-19 2019-07-31 Dow Silicones Corporation Skin contact adhesive and methods for its preparation and use
JP6816264B2 (ja) 2016-09-19 2021-01-20 ダウ シリコーンズ コーポレーション ポリウレタン−ポリオルガノシロキサンコポリマー及びその調製方法
US20210177726A1 (en) 2017-02-15 2021-06-17 Dow Silicones Corporation Personal care compositions including a polyurethane - polyorganosiloxane copolymer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4018159B2 (ja) * 1993-06-28 2007-12-05 株式会社ルネサステクノロジ 半導体集積回路
JP2697633B2 (ja) 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
JPH08329680A (ja) 1995-05-30 1996-12-13 Oki Electric Ind Co Ltd 半導体記憶装置
JP4178225B2 (ja) * 1998-06-30 2008-11-12 富士通マイクロエレクトロニクス株式会社 集積回路装置
JP2000048565A (ja) * 1998-07-29 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2001014847A (ja) 1999-06-30 2001-01-19 Toshiba Corp クロック同期回路

Also Published As

Publication number Publication date
US6826109B2 (en) 2004-11-30
US20030142526A1 (en) 2003-07-31

Similar Documents

Publication Publication Date Title
USRE41245E1 (en) Semiconductor memory device
US5717653A (en) Late-write type SRAM in which address-decoding time for reading data differs from address-decoding time for writing data
JPH0664907B2 (ja) ダイナミツク型ｒａｍ
JPH09265775A (ja) 半導体記憶装置
JP4159657B2 (ja) 同期型半導体記憶装置
KR100902125B1 (ko) 저전력 디램 및 그 구동방법
KR100230415B1 (ko) 동기식 반도체 메모리장치의 칼럼 선택라인 제어회로 및 제어방법
JPH11162161A (ja) 半導体記憶装置
US7581070B2 (en) Multi-chip package device having alternately-enabled memory chips
JP2003228982A (ja) 半導体集積回路装置
US12073911B2 (en) Apparatuses and methods for command decoding
JP3123473B2 (ja) 半導体記憶装置
KR100242453B1 (ko) 반도체 장치
US5963483A (en) Synchronous memory unit
US8107314B2 (en) Semiconductor storage device and method for producing semiconductor storage device
US6870756B2 (en) Semiconductor integrated circuit device
US5978245A (en) Associative memory device having circuitry for storing a coincidence line output
US12073912B2 (en) Apparatuses and methods for command decoding with series connected latches
US5634030A (en) Semiconductor memory device for incrementing address at high speed in burst access
US6735101B2 (en) Semiconductor memory
KR100373221B1 (ko) 동기식메모리장치
JP4327482B2 (ja) 同期型半導体記憶装置
JP2001067878A (ja) 半導体記憶装置
KR100615610B1 (ko) 반도체 메모리 장치 및 이 장치의 컬럼 인에이블 신호발생방법
KR100390238B1 (ko) 뱅크 어드레스를 이용한 반도체 메모리 소자의 어드레스제어 장치

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050128

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050128

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071106

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071114

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080402