JP2003228982A5 - - Google Patents

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Publication number
JP2003228982A5
JP2003228982A5 JP2002020721A JP2002020721A JP2003228982A5 JP 2003228982 A5 JP2003228982 A5 JP 2003228982A5 JP 2002020721 A JP2002020721 A JP 2002020721A JP 2002020721 A JP2002020721 A JP 2002020721A JP 2003228982 A5 JP2003228982 A5 JP 2003228982A5
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JP
Japan
Prior art keywords
circuit
signal
input
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002020721A
Other languages
English (en)
Japanese (ja)
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JP2003228982A (ja
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Publication date
Application filed filed Critical
Priority to JP2002020721A priority Critical patent/JP2003228982A/ja
Priority claimed from JP2002020721A external-priority patent/JP2003228982A/ja
Priority to US10/345,186 priority patent/US6826109B2/en
Publication of JP2003228982A publication Critical patent/JP2003228982A/ja
Publication of JP2003228982A5 publication Critical patent/JP2003228982A5/ja
Pending legal-status Critical Current

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JP2002020721A 2002-01-29 2002-01-29 半導体集積回路装置 Pending JP2003228982A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002020721A JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置
US10/345,186 US6826109B2 (en) 2002-01-29 2003-01-16 Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002020721A JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2003228982A JP2003228982A (ja) 2003-08-15
JP2003228982A5 true JP2003228982A5 (enExample) 2005-08-18

Family

ID=27606291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002020721A Pending JP2003228982A (ja) 2002-01-29 2002-01-29 半導体集積回路装置

Country Status (2)

Country Link
US (1) US6826109B2 (enExample)
JP (1) JP2003228982A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3948933B2 (ja) * 2001-11-07 2007-07-25 富士通株式会社 半導体記憶装置、及びその制御方法
US7443737B2 (en) 2004-03-11 2008-10-28 International Business Machines Corporation Register file
US20080168257A1 (en) * 2007-01-05 2008-07-10 Glenn Lawrence Marks Interface assembly for coupling a host to multiple storage devices
US20140184288A1 (en) * 2012-12-27 2014-07-03 Samsung Electronics Co., Ltd. Semiconductor circuit and method for operating the same
EP3515959A1 (en) 2016-09-19 2019-07-31 Dow Silicones Corporation Skin contact adhesive and methods for its preparation and use
JP6816264B2 (ja) 2016-09-19 2021-01-20 ダウ シリコーンズ コーポレーション ポリウレタン−ポリオルガノシロキサンコポリマー及びその調製方法
US20210177726A1 (en) 2017-02-15 2021-06-17 Dow Silicones Corporation Personal care compositions including a polyurethane - polyorganosiloxane copolymer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4018159B2 (ja) * 1993-06-28 2007-12-05 株式会社ルネサステクノロジ 半導体集積回路
JP2697633B2 (ja) 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
JPH08329680A (ja) 1995-05-30 1996-12-13 Oki Electric Ind Co Ltd 半導体記憶装置
JP4178225B2 (ja) * 1998-06-30 2008-11-12 富士通マイクロエレクトロニクス株式会社 集積回路装置
JP2000048565A (ja) * 1998-07-29 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2001014847A (ja) 1999-06-30 2001-01-19 Toshiba Corp クロック同期回路

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