JP2003142584A5 - - Google Patents

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Publication number
JP2003142584A5
JP2003142584A5 JP2001339024A JP2001339024A JP2003142584A5 JP 2003142584 A5 JP2003142584 A5 JP 2003142584A5 JP 2001339024 A JP2001339024 A JP 2001339024A JP 2001339024 A JP2001339024 A JP 2001339024A JP 2003142584 A5 JP2003142584 A5 JP 2003142584A5
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JP
Japan
Prior art keywords
reference value
mask data
error
opc mask
chip
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Pending
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JP2001339024A
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English (en)
Japanese (ja)
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JP2003142584A (ja
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Priority to JP2001339024A priority Critical patent/JP2003142584A/ja
Priority claimed from JP2001339024A external-priority patent/JP2003142584A/ja
Priority to US10/281,300 priority patent/US6871338B2/en
Publication of JP2003142584A publication Critical patent/JP2003142584A/ja
Publication of JP2003142584A5 publication Critical patent/JP2003142584A5/ja
Pending legal-status Critical Current

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JP2001339024A 2001-11-05 2001-11-05 半導体集積回路装置の設計方法 Pending JP2003142584A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001339024A JP2003142584A (ja) 2001-11-05 2001-11-05 半導体集積回路装置の設計方法
US10/281,300 US6871338B2 (en) 2001-11-05 2002-10-28 Semiconductor integrated circuit device and method for designing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001339024A JP2003142584A (ja) 2001-11-05 2001-11-05 半導体集積回路装置の設計方法

Publications (2)

Publication Number Publication Date
JP2003142584A JP2003142584A (ja) 2003-05-16
JP2003142584A5 true JP2003142584A5 (enExample) 2005-05-26

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Family Applications (1)

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JP2001339024A Pending JP2003142584A (ja) 2001-11-05 2001-11-05 半導体集積回路装置の設計方法

Country Status (2)

Country Link
US (1) US6871338B2 (enExample)
JP (1) JP2003142584A (enExample)

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US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7794897B2 (en) 2004-03-02 2010-09-14 Kabushiki Kaisha Toshiba Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US7340713B2 (en) * 2004-09-29 2008-03-04 Synopsys, Inc. Method and apparatus for determining a proximity correction using a visible area model
US7337415B2 (en) * 2004-10-18 2008-02-26 International Business Machines Corporation Systematic yield in semiconductor manufacture
US20060199087A1 (en) * 2005-03-03 2006-09-07 Lucas Kevin D Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field
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US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
JP4715760B2 (ja) * 2006-07-28 2011-07-06 株式会社デンソー マイクロコンピュータ及び制御システム
WO2008020266A1 (en) * 2006-08-16 2008-02-21 Freescale Semiconductor, Inc. Method and apparatus for designing an integrated circuit
JP4745256B2 (ja) * 2007-01-26 2011-08-10 株式会社東芝 パターン作成方法、パターン作成・検証プログラム、および半導体装置の製造方法
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8010912B2 (en) * 2007-03-09 2011-08-30 Broadcom Corporation Method of shrinking semiconductor mask features for process improvement
US8112724B2 (en) * 2007-03-20 2012-02-07 Sony Corporation Method of designing semiconductor integrated circuit, apparatus for designing semiconductor integrated circuit, recording medium, and mask manufacturing method
JP4333799B2 (ja) * 2007-03-20 2009-09-16 ソニー株式会社 半導体集積回路の設計方法、半導体集積回路の設計装置、記録媒体、およびマスク製造方法
JP4996972B2 (ja) * 2007-05-21 2012-08-08 ルネサスエレクトロニクス株式会社 マスクデータ生成方法およびマスクデータ生成システム
JP2009099044A (ja) 2007-10-18 2009-05-07 Toshiba Corp パターンデータ作成方法、設計レイアウト作成方法及びパターンデータ検証方法
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US20110047519A1 (en) * 2009-05-11 2011-02-24 Juan Andres Torres Robles Layout Content Analysis for Source Mask Optimization Acceleration
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP5530804B2 (ja) * 2010-05-17 2014-06-25 パナソニック株式会社 半導体装置、半導体装置製造用マスク及び光近接効果補正方法
JP2012027058A (ja) * 2010-07-20 2012-02-09 Fujitsu Semiconductor Ltd パターンデータ生成プログラム及びパターンデータ生成装置
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
CN103472672B (zh) * 2012-06-06 2016-01-06 中芯国际集成电路制造(上海)有限公司 校正光学邻近校正模型的方法
US20170186500A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Memory circuit defect correction
KR102417183B1 (ko) 2016-02-25 2022-07-05 삼성전자주식회사 적층형 메모리 장치, ｏｐｃ 검증 방법, 적층형 메모리 장치의 레이아웃 디자인 방법, 및 적층형 메모리 장치의 제조 방법
TWI704421B (zh) * 2016-06-10 2020-09-11 比利時商愛美科公司 半導體製程的量測方法
CN109031880B (zh) * 2018-07-13 2022-03-18 上海华力集成电路制造有限公司 Sram版图的opc修正方法
CN112859508B (zh) * 2019-11-27 2024-11-01 台湾积体电路制造股份有限公司 集成电路制造方法

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Publication number Priority date Publication date Assignee Title
JP3934719B2 (ja) 1995-12-22 2007-06-20 株式会社東芝 光近接効果補正方法
US6282696B1 (en) * 1997-08-15 2001-08-28 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
US6470489B1 (en) * 1997-09-17 2002-10-22 Numerical Technologies, Inc. Design rule checking system and method
US6245468B1 (en) 1999-10-27 2001-06-12 Micron Technology, Inc. Optical proximity correction methods, and methods of forming radiation-patterning tools
US6625801B1 (en) * 2000-09-29 2003-09-23 Numerical Technologies, Inc. Dissection of printed edges from a fabrication layout for correcting proximity effects
US6553559B2 (en) * 2001-01-05 2003-04-22 International Business Machines Corporation Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions

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