JP2003124801A5 - - Google Patents

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Publication number
JP2003124801A5
JP2003124801A5 JP2002222365A JP2002222365A JP2003124801A5 JP 2003124801 A5 JP2003124801 A5 JP 2003124801A5 JP 2002222365 A JP2002222365 A JP 2002222365A JP 2002222365 A JP2002222365 A JP 2002222365A JP 2003124801 A5 JP2003124801 A5 JP 2003124801A5
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JP
Japan
Prior art keywords
data
sense amplifier
manipulation method
clock
transition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002222365A
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English (en)
Japanese (ja)
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JP2003124801A (ja
JP3872733B2 (ja
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Publication date
Priority claimed from US09/927,673 external-priority patent/US6476645B1/en
Application filed filed Critical
Publication of JP2003124801A publication Critical patent/JP2003124801A/ja
Publication of JP2003124801A5 publication Critical patent/JP2003124801A5/ja
Application granted granted Critical
Publication of JP3872733B2 publication Critical patent/JP3872733B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2002222365A 2001-08-10 2002-07-31 絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置 Expired - Fee Related JP3872733B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/927673 2001-08-10
US09/927,673 US6476645B1 (en) 2001-08-10 2001-08-10 Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit

Publications (3)

Publication Number Publication Date
JP2003124801A JP2003124801A (ja) 2003-04-25
JP2003124801A5 true JP2003124801A5 (enExample) 2005-06-23
JP3872733B2 JP3872733B2 (ja) 2007-01-24

Family

ID=25455072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002222365A Expired - Fee Related JP3872733B2 (ja) 2001-08-10 2002-07-31 絶縁体上シリコン（ｓｏｉ）ベースの回路における履歴効果を緩和するための方法及び装置

Country Status (2)

Country Link
US (2) US6476645B1 (enExample)
JP (1) JP3872733B2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100455398B1 (ko) * 2002-12-13 2004-11-06 삼성전자주식회사 동작 속도가 향상된 데이터 래치 회로.
US6833737B2 (en) * 2003-01-30 2004-12-21 International Business Machines Corporation SOI sense amplifier method and apparatus
US6995598B2 (en) * 2003-02-13 2006-02-07 Texas Instruments Incorporated Level shifter circuit including a set/reset circuit
US6819155B1 (en) 2003-06-23 2004-11-16 Teradyne, Inc. High-speed duty cycle control circuit
DE10331544B3 (de) * 2003-07-11 2004-09-30 Infineon Technologies Ag Verfahren zum Ansteuern eines Transistors
WO2005029704A1 (en) * 2003-09-17 2005-03-31 The Regents Of The University Of California A dynamic and differential cmos logic with signal-independent power consumption to withstand differential power analysis
US20050162193A1 (en) * 2004-01-27 2005-07-28 Texas Instruments Incorporated High performance sense amplifiers
CN101527133B (zh) 2004-09-17 2012-07-18 日本电气株式会社 半导体器件、使用该器件的电路和显示设备及其驱动方法
KR100699862B1 (ko) * 2005-08-26 2007-03-27 삼성전자주식회사 반도체 장치의 이중 기준 입력 수신기 및 이의 입력 데이터신호 수신방법
US7333379B2 (en) * 2006-01-12 2008-02-19 International Business Machines Corporation Balanced sense amplifier circuits with adjustable transistor body bias
KR100771878B1 (ko) * 2006-08-09 2007-11-01 삼성전자주식회사 세미-듀얼 기준전압을 이용한 데이터 수신 장치
US7564266B2 (en) * 2007-06-25 2009-07-21 Qualcomm Incorporated Logic state catching circuits
US8067917B2 (en) * 2008-04-08 2011-11-29 Liebert Corporation Hysteresis mitigation and control method
WO2010005343A2 (en) * 2008-07-08 2010-01-14 Marat Vadimovich Evtukhov Rebreather respiratory loop failure detector
US8130567B2 (en) 2008-12-24 2012-03-06 Stmicroelectronics Pvt. Ltd. Write circuitry for hierarchical memory architecture
US8108816B2 (en) * 2009-06-15 2012-01-31 International Business Machines Corporation Device history based delay variation adjustment during static timing analysis
US8141014B2 (en) * 2009-08-10 2012-03-20 International Business Machines Corporation System and method for common history pessimism relief during static timing analysis
JP2012227588A (ja) * 2011-04-15 2012-11-15 Fujitsu Semiconductor Ltd 比較回路及びアナログデジタル変換回路
US9443567B1 (en) * 2015-04-16 2016-09-13 Intel Corporation High speed sense amplifier latch with low power rail-to-rail input common mode range
KR20170045542A (ko) * 2015-10-19 2017-04-27 삼성전자주식회사 에지 검출기 및 이를 포함하는 신호 특성 분석 시스템
US11328771B2 (en) * 2020-09-15 2022-05-10 Integrated Silicon Solution, (Cayman) Inc. Sense amplifier circuit for preventing read disturb

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1238022B (it) * 1989-12-22 1993-06-23 Cselt Centro Studi Lab Telecom Discriminatore differenziale di tensione in tecnologia c-mos.
KR100223675B1 (ko) * 1996-12-30 1999-10-15 윤종용 고속동작용 반도체 메모리 장치에 적합한 데이터 출력관련 회로
US5929660A (en) * 1997-12-29 1999-07-27 United Technologies Corporation Dynamic, single-ended sense amplifier
US6188259B1 (en) * 1999-11-03 2001-02-13 Sun Microsystems, Inc. Self-reset flip-flop with self shut-off mechanism
US6288932B1 (en) * 2000-04-25 2001-09-11 Sun Microsystems, Inc. Dynamic flop with power down mode
US6608789B2 (en) * 2001-12-21 2003-08-19 Motorola, Inc. Hysteresis reduced sense amplifier and method of operation

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