JP2003022215A5 - - Google Patents

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Publication number
JP2003022215A5
JP2003022215A5 JP2002141409A JP2002141409A JP2003022215A5 JP 2003022215 A5 JP2003022215 A5 JP 2003022215A5 JP 2002141409 A JP2002141409 A JP 2002141409A JP 2002141409 A JP2002141409 A JP 2002141409A JP 2003022215 A5 JP2003022215 A5 JP 2003022215A5
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JP
Japan
Prior art keywords
column
access
write
memory
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002141409A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003022215A (ja
Filing date
Publication date
Priority claimed from US09/870,361 external-priority patent/US6587917B2/en
Application filed filed Critical
Publication of JP2003022215A publication Critical patent/JP2003022215A/ja
Publication of JP2003022215A5 publication Critical patent/JP2003022215A5/ja
Withdrawn legal-status Critical Current

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JP2002141409A 2001-05-29 2002-05-16 異なるタイプの並行メモリ・アクセスを支援するための方法 Withdrawn JP2003022215A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/870,361 2001-05-29
US09/870,361 US6587917B2 (en) 2001-05-29 2001-05-29 Memory architecture for supporting concurrent access of different types

Publications (2)

Publication Number Publication Date
JP2003022215A JP2003022215A (ja) 2003-01-24
JP2003022215A5 true JP2003022215A5 (enExample) 2005-09-22

Family

ID=25355216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002141409A Withdrawn JP2003022215A (ja) 2001-05-29 2002-05-16 異なるタイプの並行メモリ・アクセスを支援するための方法

Country Status (5)

Country Link
US (1) US6587917B2 (enExample)
EP (1) EP1262990A1 (enExample)
JP (1) JP2003022215A (enExample)
KR (1) KR100902473B1 (enExample)
TW (1) TW550591B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1537229A (zh) * 2001-07-31 2004-10-13 ���ְ�˹��ʽ���� 基因检查装置和使用该装置检测靶核酸的方法
JP3793062B2 (ja) * 2001-09-27 2006-07-05 株式会社東芝 メモリ内蔵データ処理装置
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US8233322B2 (en) * 2003-10-10 2012-07-31 Micron Technology, Inc. Multi-partition memory with separated read and algorithm datalines
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9477597B2 (en) 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9135982B2 (en) * 2013-12-18 2015-09-15 Intel Corporation Techniques for accessing a dynamic random access memory array
US10055236B2 (en) * 2015-07-02 2018-08-21 Sandisk Technologies Llc Runtime data storage and/or retrieval

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643236A (en) * 1969-12-19 1972-02-15 Ibm Storage having a plurality of simultaneously accessible locations
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
KR940008295B1 (ko) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 반도체메모리
JP3532932B2 (ja) * 1991-05-20 2004-05-31 モトローラ・インコーポレイテッド 時間重複メモリ・アクセスを有するランダムにアクセス可能なメモリ
US5276642A (en) * 1991-07-15 1994-01-04 Micron Technology, Inc. Method for performing a split read/write operation in a dynamic random access memory
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
JPH08235852A (ja) * 1995-02-28 1996-09-13 Mitsubishi Electric Corp 半導体記憶装置
JP3567043B2 (ja) * 1996-03-07 2004-09-15 株式会社ルネサステクノロジ 半導体記憶装置
JPH1031886A (ja) * 1996-07-17 1998-02-03 Nec Corp ランダムアクセスメモリ
US6157560A (en) * 1999-01-25 2000-12-05 Winbond Electronics Corporation Memory array datapath architecture
US6377492B1 (en) * 2001-03-19 2002-04-23 Etron Technologies, Inc. Memory architecture for read and write at the same time using a conventional cell
JP2009122495A (ja) * 2007-11-16 2009-06-04 Sun Tec Kk 波長選択性光減衰器

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