KR100902473B1 - 혼합 모드 메모리 액세스의 수행 방법 및 메모리 - Google Patents

혼합 모드 메모리 액세스의 수행 방법 및 메모리 Download PDF

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Publication number
KR100902473B1
KR100902473B1 KR1020020029510A KR20020029510A KR100902473B1 KR 100902473 B1 KR100902473 B1 KR 100902473B1 KR 1020020029510 A KR1020020029510 A KR 1020020029510A KR 20020029510 A KR20020029510 A KR 20020029510A KR 100902473 B1 KR100902473 B1 KR 100902473B1
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South Korea
Prior art keywords
column
access
memory
row
write
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KR1020020029510A
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English (en)
Korean (ko)
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KR20020090904A (ko
Inventor
시먼스라우라엘리자베스
Original Assignee
아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드
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Publication of KR20020090904A publication Critical patent/KR20020090904A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
KR1020020029510A 2001-05-29 2002-05-28 혼합 모드 메모리 액세스의 수행 방법 및 메모리 Expired - Fee Related KR100902473B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/870,361 US6587917B2 (en) 2001-05-29 2001-05-29 Memory architecture for supporting concurrent access of different types
US09/870,361 2001-05-29

Publications (2)

Publication Number Publication Date
KR20020090904A KR20020090904A (ko) 2002-12-05
KR100902473B1 true KR100902473B1 (ko) 2009-06-11

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KR1020020029510A Expired - Fee Related KR100902473B1 (ko) 2001-05-29 2002-05-28 혼합 모드 메모리 액세스의 수행 방법 및 메모리

Country Status (5)

Country Link
US (1) US6587917B2 (enExample)
EP (1) EP1262990A1 (enExample)
JP (1) JP2003022215A (enExample)
KR (1) KR100902473B1 (enExample)
TW (1) TW550591B (enExample)

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* Cited by examiner, † Cited by third party
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JPWO2003027673A1 (ja) * 2001-07-31 2005-01-13 オリンパス株式会社 遺伝子検査装置およびそれを用いた標的核酸検出方法
JP3793062B2 (ja) * 2001-09-27 2006-07-05 株式会社東芝 メモリ内蔵データ処理装置
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US8233322B2 (en) * 2003-10-10 2012-07-31 Micron Technology, Inc. Multi-partition memory with separated read and algorithm datalines
US7280428B2 (en) * 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US9477597B2 (en) 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9135982B2 (en) * 2013-12-18 2015-09-15 Intel Corporation Techniques for accessing a dynamic random access memory array
US10055236B2 (en) * 2015-07-02 2018-08-21 Sandisk Technologies Llc Runtime data storage and/or retrieval

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09245473A (ja) * 1996-03-07 1997-09-19 Hitachi Ltd 半導体記憶装置

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
US3638204A (en) * 1969-12-19 1972-01-25 Ibm Semiconductive cell for a storage having a plurality of simultaneously accessible locations
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
KR940008295B1 (ko) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 반도체메모리
JP3532932B2 (ja) * 1991-05-20 2004-05-31 モトローラ・インコーポレイテッド 時間重複メモリ・アクセスを有するランダムにアクセス可能なメモリ
US5276642A (en) * 1991-07-15 1994-01-04 Micron Technology, Inc. Method for performing a split read/write operation in a dynamic random access memory
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
JPH08235852A (ja) * 1995-02-28 1996-09-13 Mitsubishi Electric Corp 半導体記憶装置
JPH1031886A (ja) * 1996-07-17 1998-02-03 Nec Corp ランダムアクセスメモリ
US6157560A (en) * 1999-01-25 2000-12-05 Winbond Electronics Corporation Memory array datapath architecture
US6377492B1 (en) * 2001-03-19 2002-04-23 Etron Technologies, Inc. Memory architecture for read and write at the same time using a conventional cell
JP2009122495A (ja) * 2007-11-16 2009-06-04 Sun Tec Kk 波長選択性光減衰器

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09245473A (ja) * 1996-03-07 1997-09-19 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
TW550591B (en) 2003-09-01
US6587917B2 (en) 2003-07-01
JP2003022215A (ja) 2003-01-24
KR20020090904A (ko) 2002-12-05
EP1262990A1 (en) 2002-12-04
US20020184437A1 (en) 2002-12-05

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