JP2002533813A5 - - Google Patents

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Publication number
JP2002533813A5
JP2002533813A5 JP2000590062A JP2000590062A JP2002533813A5 JP 2002533813 A5 JP2002533813 A5 JP 2002533813A5 JP 2000590062 A JP2000590062 A JP 2000590062A JP 2000590062 A JP2000590062 A JP 2000590062A JP 2002533813 A5 JP2002533813 A5 JP 2002533813A5
Authority
JP
Japan
Prior art keywords
processing node
response
memory
computer system
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000590062A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002533813A (ja
JP4718012B2 (ja
Filing date
Publication date
Priority claimed from US09/217,649 external-priority patent/US6275905B1/en
Priority claimed from US09/217,699 external-priority patent/US6370621B1/en
Priority claimed from US09/217,212 external-priority patent/US6490661B1/en
Priority claimed from US09/370,970 external-priority patent/US6393529B1/en
Application filed filed Critical
Priority claimed from PCT/US1999/019856 external-priority patent/WO2000038070A1/en
Publication of JP2002533813A publication Critical patent/JP2002533813A/ja
Publication of JP2002533813A5 publication Critical patent/JP2002533813A5/ja
Application granted granted Critical
Publication of JP4718012B2 publication Critical patent/JP4718012B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2000590062A 1998-12-21 1999-08-26 メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持 Expired - Lifetime JP4718012B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US09/217,699 1998-12-21
US09/217,649 US6275905B1 (en) 1998-12-21 1998-12-21 Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
US09/217,212 1998-12-21
US09/217,699 US6370621B1 (en) 1998-12-21 1998-12-21 Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US09/217,649 1998-12-21
US09/217,212 US6490661B1 (en) 1998-12-21 1998-12-21 Maintaining cache coherency during a memory read operation in a multiprocessing computer system
US09/370,970 US6393529B1 (en) 1998-12-21 1999-08-10 Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write
US09/370,970 1999-08-10
PCT/US1999/019856 WO2000038070A1 (en) 1998-12-21 1999-08-26 Conservation of system memory bandwidth and cache coherency maintenance using memory cancel messages

Publications (3)

Publication Number Publication Date
JP2002533813A JP2002533813A (ja) 2002-10-08
JP2002533813A5 true JP2002533813A5 (enExample) 2006-09-07
JP4718012B2 JP4718012B2 (ja) 2011-07-06

Family

ID=27499064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000590062A Expired - Lifetime JP4718012B2 (ja) 1998-12-21 1999-08-26 メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持

Country Status (4)

Country Link
EP (2) EP2320322A3 (enExample)
JP (1) JP4718012B2 (enExample)
KR (1) KR100615660B1 (enExample)
WO (1) WO2000038070A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6631401B1 (en) * 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6799217B2 (en) * 2001-06-04 2004-09-28 Fujitsu Limited Shared memory multiprocessor expansion port for multi-node systems
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
JP4572169B2 (ja) * 2006-01-26 2010-10-27 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム及びその動作方法
EP2650794A1 (en) * 2010-12-06 2013-10-16 Fujitsu Limited Information processing system and information transmission method
US11159636B2 (en) * 2017-02-08 2021-10-26 Arm Limited Forwarding responses to snoop requests

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5864846A (ja) * 1981-10-15 1983-04-18 Hitachi Ltd デ−タ伝送制御装置
JPS60200351A (ja) * 1984-03-26 1985-10-09 Hitachi Ltd 記憶制御方式
JPS63223948A (ja) * 1987-03-13 1988-09-19 Toyo Commun Equip Co Ltd マルチプロセツサｏｓに於けるプロセツサ間通信方法
JPH02205963A (ja) * 1989-01-27 1990-08-15 Digital Equip Corp <Dec> 読取中断処理
EP0412353A3 (en) * 1989-08-11 1992-05-27 Hitachi, Ltd. Multiprocessor cache system having three states for generating invalidating signals upon write accesses
JPH04113444A (ja) * 1990-09-04 1992-04-14 Oki Electric Ind Co Ltd 双方向リングバス装置
FR2680026B1 (fr) * 1991-07-30 1996-12-20 Commissariat Energie Atomique Architecture de systeme en tableau de processeurs a structure parallele.
CA2078312A1 (en) * 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
JPH05134991A (ja) * 1991-11-11 1993-06-01 Yokogawa Electric Corp 密結合型マルチプロセツサシステム
JPH06110844A (ja) * 1992-08-11 1994-04-22 Toshiba Corp 分散共有メモリ型マルチプロセッサシステム
US5590307A (en) * 1993-01-05 1996-12-31 Sgs-Thomson Microelectronics, Inc. Dual-port data cache memory
JP2819982B2 (ja) * 1993-03-18 1998-11-05 株式会社日立製作所 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム
JPH06314239A (ja) * 1993-04-28 1994-11-08 Hitachi Ltd プロセッサシステム
JPH0816474A (ja) * 1994-06-29 1996-01-19 Hitachi Ltd マルチプロセッサシステム
JPH0991262A (ja) * 1995-09-20 1997-04-04 Fuji Xerox Co Ltd マルチプロセッサシステム
US5659710A (en) * 1995-11-29 1997-08-19 International Business Machines Corporation Cache coherency method and system employing serially encoded snoop responses
US5893160A (en) * 1996-04-08 1999-04-06 Sun Microsystems, Inc. Deterministic distributed multi-cache coherence method and system
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US6038651A (en) * 1998-03-23 2000-03-14 International Business Machines Corporation SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum
JP2000132531A (ja) * 1998-10-23 2000-05-12 Pfu Ltd マルチプロセッサ
US6631401B1 (en) * 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency

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