KR100615660B1 - 메모리 취소 메세지를 이용한 시스템 메모리 대역폭의유지 및 캐시 코히런시 유지 - Google Patents

메모리 취소 메세지를 이용한 시스템 메모리 대역폭의유지 및 캐시 코히런시 유지 Download PDF

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KR100615660B1
KR100615660B1 KR1020017007742A KR20017007742A KR100615660B1 KR 100615660 B1 KR100615660 B1 KR 100615660B1 KR 1020017007742 A KR1020017007742 A KR 1020017007742A KR 20017007742 A KR20017007742 A KR 20017007742A KR 100615660 B1 KR100615660 B1 KR 100615660B1
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processing node
response
memory
node
read
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Korean (ko)
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KR20010082376A (ko
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켈러제임스비.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Priority claimed from US09/217,649 external-priority patent/US6275905B1/en
Priority claimed from US09/217,699 external-priority patent/US6370621B1/en
Priority claimed from US09/217,212 external-priority patent/US6490661B1/en
Priority claimed from US09/370,970 external-priority patent/US6393529B1/en
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
KR1020017007742A 1998-12-21 1999-08-26 메모리 취소 메세지를 이용한 시스템 메모리 대역폭의유지 및 캐시 코히런시 유지 Expired - Lifetime KR100615660B1 (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US09/217,699 1998-12-21
US09/217,649 US6275905B1 (en) 1998-12-21 1998-12-21 Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system
US09/217,212 1998-12-21
US09/217,699 US6370621B1 (en) 1998-12-21 1998-12-21 Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US09/217,649 1998-12-21
US09/217,212 US6490661B1 (en) 1998-12-21 1998-12-21 Maintaining cache coherency during a memory read operation in a multiprocessing computer system
US09/370,970 US6393529B1 (en) 1998-12-21 1999-08-10 Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write
US09/370,970 1999-08-10

Publications (2)

Publication Number Publication Date
KR20010082376A KR20010082376A (ko) 2001-08-29
KR100615660B1 true KR100615660B1 (ko) 2006-08-25

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KR1020017007742A Expired - Lifetime KR100615660B1 (ko) 1998-12-21 1999-08-26 메모리 취소 메세지를 이용한 시스템 메모리 대역폭의유지 및 캐시 코히런시 유지

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EP (2) EP2320322A3 (enExample)
JP (1) JP4718012B2 (enExample)
KR (1) KR100615660B1 (enExample)
WO (1) WO2000038070A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6631401B1 (en) * 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6799217B2 (en) * 2001-06-04 2004-09-28 Fujitsu Limited Shared memory multiprocessor expansion port for multi-node systems
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
JP4572169B2 (ja) * 2006-01-26 2010-10-27 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム及びその動作方法
EP2650794A1 (en) * 2010-12-06 2013-10-16 Fujitsu Limited Information processing system and information transmission method
US11159636B2 (en) * 2017-02-08 2021-10-26 Arm Limited Forwarding responses to snoop requests

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02205963A (ja) * 1989-01-27 1990-08-15 Digital Equip Corp <Dec> 読取中断処理

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JPS5864846A (ja) * 1981-10-15 1983-04-18 Hitachi Ltd デ−タ伝送制御装置
JPS60200351A (ja) * 1984-03-26 1985-10-09 Hitachi Ltd 記憶制御方式
JPS63223948A (ja) * 1987-03-13 1988-09-19 Toyo Commun Equip Co Ltd マルチプロセツサｏｓに於けるプロセツサ間通信方法
EP0412353A3 (en) * 1989-08-11 1992-05-27 Hitachi, Ltd. Multiprocessor cache system having three states for generating invalidating signals upon write accesses
JPH04113444A (ja) * 1990-09-04 1992-04-14 Oki Electric Ind Co Ltd 双方向リングバス装置
FR2680026B1 (fr) * 1991-07-30 1996-12-20 Commissariat Energie Atomique Architecture de systeme en tableau de processeurs a structure parallele.
CA2078312A1 (en) * 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
JPH05134991A (ja) * 1991-11-11 1993-06-01 Yokogawa Electric Corp 密結合型マルチプロセツサシステム
JPH06110844A (ja) * 1992-08-11 1994-04-22 Toshiba Corp 分散共有メモリ型マルチプロセッサシステム
US5590307A (en) * 1993-01-05 1996-12-31 Sgs-Thomson Microelectronics, Inc. Dual-port data cache memory
JP2819982B2 (ja) * 1993-03-18 1998-11-05 株式会社日立製作所 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム
JPH06314239A (ja) * 1993-04-28 1994-11-08 Hitachi Ltd プロセッサシステム
JPH0816474A (ja) * 1994-06-29 1996-01-19 Hitachi Ltd マルチプロセッサシステム
JPH0991262A (ja) * 1995-09-20 1997-04-04 Fuji Xerox Co Ltd マルチプロセッサシステム
US5659710A (en) * 1995-11-29 1997-08-19 International Business Machines Corporation Cache coherency method and system employing serially encoded snoop responses
US5893160A (en) * 1996-04-08 1999-04-06 Sun Microsystems, Inc. Deterministic distributed multi-cache coherence method and system
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US6038651A (en) * 1998-03-23 2000-03-14 International Business Machines Corporation SMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimum
JP2000132531A (ja) * 1998-10-23 2000-05-12 Pfu Ltd マルチプロセッサ
US6631401B1 (en) * 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency

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JPH02205963A (ja) * 1989-01-27 1990-08-15 Digital Equip Corp <Dec> 読取中断処理

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Publication number Publication date
JP2002533813A (ja) 2002-10-08
KR20010082376A (ko) 2001-08-29
JP4718012B2 (ja) 2011-07-06
WO2000038070A1 (en) 2000-06-29
EP2320322A3 (en) 2011-08-03
EP1141838A1 (en) 2001-10-10
EP2320322A2 (en) 2011-05-11

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