JP2002501276A5 - - Google Patents

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Publication number
JP2002501276A5
JP2002501276A5 JP2000527946A JP2000527946A JP2002501276A5 JP 2002501276 A5 JP2002501276 A5 JP 2002501276A5 JP 2000527946 A JP2000527946 A JP 2000527946A JP 2000527946 A JP2000527946 A JP 2000527946A JP 2002501276 A5 JP2002501276 A5 JP 2002501276A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000527946A
Other languages
Japanese (ja)
Other versions
JP2002501276A (ja
JP4414087B2 (ja
Filing date
Publication date
Priority claimed from US09/002,649 external-priority patent/US6088264A/en
Application filed filed Critical
Publication of JP2002501276A publication Critical patent/JP2002501276A/ja
Publication of JP2002501276A5 publication Critical patent/JP2002501276A5/ja
Application granted granted Critical
Publication of JP4414087B2 publication Critical patent/JP4414087B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000527946A 1998-01-05 1998-11-24 読取り同時書込み操作のためのフラッシュ・メモリ分割 Expired - Fee Related JP4414087B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/002,649 US6088264A (en) 1998-01-05 1998-01-05 Flash memory partitioning for read-while-write operation
US09/002,649 1998-01-05
PCT/US1998/025217 WO1999035650A1 (en) 1998-01-05 1998-11-24 Flash memory partitioning for read-while-write operation

Publications (3)

Publication Number Publication Date
JP2002501276A JP2002501276A (ja) 2002-01-15
JP2002501276A5 true JP2002501276A5 (enExample) 2006-01-19
JP4414087B2 JP4414087B2 (ja) 2010-02-10

Family

ID=21701801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000527946A Expired - Fee Related JP4414087B2 (ja) 1998-01-05 1998-11-24 読取り同時書込み操作のためのフラッシュ・メモリ分割

Country Status (8)

Country Link
US (1) US6088264A (enExample)
JP (1) JP4414087B2 (enExample)
KR (1) KR100388949B1 (enExample)
AU (1) AU1536899A (enExample)
DE (1) DE19882933B4 (enExample)
GB (1) GB2347767B (enExample)
TW (1) TW455911B (enExample)
WO (1) WO1999035650A1 (enExample)

Families Citing this family (41)

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US6345000B1 (en) 1997-04-16 2002-02-05 Sandisk Corporation Flash memory permitting simultaneous read/write and erase operations in a single memory array
US6591327B1 (en) * 1999-06-22 2003-07-08 Silicon Storage Technology, Inc. Flash memory with alterable erase sector size
EP1073064A1 (en) * 1999-07-30 2001-01-31 STMicroelectronics S.r.l. Non-volatile memory with the functional capability of simultaneous modification of the contents and burst mode read or page mode read
US6407949B1 (en) 1999-12-17 2002-06-18 Qualcomm, Incorporated Mobile communication device having integrated embedded flash and SRAM memory
US6662263B1 (en) 2000-03-03 2003-12-09 Multi Level Memory Technology Sectorless flash memory architecture
US6240040B1 (en) * 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
US6851026B1 (en) * 2000-07-28 2005-02-01 Micron Technology, Inc. Synchronous flash memory with concurrent write and read operation
FR2809223A1 (fr) * 2000-05-17 2001-11-23 Schlumberger Systems & Service Effacement d'eeprom en temps masque
US6772273B1 (en) * 2000-06-29 2004-08-03 Intel Corporation Block-level read while write method and apparatus
US6748482B1 (en) 2000-09-27 2004-06-08 Intel Corporation Multiple non-contiguous block erase in flash memory
EP1201899B1 (en) * 2000-10-16 2006-04-05 STMicroelectronics S.r.l. A control device for a vehicle motor
US6931498B2 (en) * 2001-04-03 2005-08-16 Intel Corporation Status register architecture for flexible read-while-write device
US6584034B1 (en) * 2001-04-23 2003-06-24 Aplus Flash Technology Inc. Flash memory array structure suitable for multiple simultaneous operations
US7062616B2 (en) * 2001-06-12 2006-06-13 Intel Corporation Implementing a dual partition flash with suspend/resume capabilities
JP3827540B2 (ja) * 2001-06-28 2006-09-27 シャープ株式会社 不揮発性半導体記憶装置および情報機器
US6628563B1 (en) 2001-07-09 2003-09-30 Aplus Flash Technology, Inc. Flash memory array for multiple simultaneous operations
US6614685B2 (en) 2001-08-09 2003-09-02 Multi Level Memory Technology Flash memory array partitioning architectures
US6781914B2 (en) 2001-08-23 2004-08-24 Winbond Electronics Corp. Flash memory having a flexible bank partition
US7177197B2 (en) 2001-09-17 2007-02-13 Sandisk Corporation Latched programming of memory and method
US6741502B1 (en) * 2001-09-17 2004-05-25 Sandisk Corporation Background operation for memory cells
US7562208B1 (en) * 2002-02-07 2009-07-14 Network Appliance, Inc. Method and system to quarantine system software and configuration
EP1376608A1 (fr) * 2002-06-28 2004-01-02 Cp8 Procédé d'écriture dans une mémoire non volatile et système pour la mise en oeuvre d'un tel procédé
JP4101583B2 (ja) * 2002-08-08 2008-06-18 富士通株式会社 消去動作時間を短縮したフラッシュメモリ
CN100433194C (zh) * 2002-12-10 2008-11-12 华邦电子股份有限公司 具有弹性排区分区的闪存及形成方法
KR101107288B1 (ko) * 2003-12-17 2012-01-20 엘지전자 주식회사 다중 분할된 플래시 메모리 장치 및 분할된 메모리에데이터를 저장하기 위한 이중 저널링 저장방법
US7388789B2 (en) * 2005-08-31 2008-06-17 Micron Technology NAND memory device and programming methods
US7292473B2 (en) * 2005-09-07 2007-11-06 Freescale Semiconductor, Inc. Method and apparatus for programming/erasing a non-volatile memory
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7562180B2 (en) 2006-03-28 2009-07-14 Nokia Corporation Method and device for reduced read latency of non-volatile memory
US7573744B2 (en) * 2006-09-29 2009-08-11 Kabushiki Kaisha Toshiba Semiconductor memory device having different capacity areas
JP4996277B2 (ja) 2007-02-09 2012-08-08 株式会社東芝 半導体記憶システム
US7613051B2 (en) * 2007-03-14 2009-11-03 Apple Inc. Interleaving charge pumps for programmable memories
EP2248130A1 (en) * 2008-02-19 2010-11-10 Rambus Inc. Multi-bank flash memory architecture with assignable resources
WO2011128867A1 (en) 2010-04-15 2011-10-20 Ramot At Tel Aviv University Ltd. Multiple programming of flash memory without erase
JP5412576B2 (ja) * 2010-04-19 2014-02-12 パナソニック株式会社 コンテンツ受信端末、およびエキスポート再生方法
KR20120015725A (ko) 2010-08-13 2012-02-22 삼성전자주식회사 전압 제어 방법 및 이를 이용한 메모리 장치
US9496046B1 (en) 2015-08-14 2016-11-15 Integrated Silicon Solution, Inc. High speed sequential read method for flash memory
KR102425259B1 (ko) 2015-11-27 2022-07-27 에스케이하이닉스 주식회사 비휘발성 메모리 장치, 반도체 장치 및 반도체 장치의 동작 방법
JP6753746B2 (ja) 2016-09-15 2020-09-09 キオクシア株式会社 半導体記憶装置
US10719248B2 (en) * 2018-04-20 2020-07-21 Micron Technology, Inc. Apparatuses and methods for counter update operations
TWI796148B (zh) 2022-02-25 2023-03-11 華邦電子股份有限公司 快閃記憶體抹除方法

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US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5361227A (en) * 1991-12-19 1994-11-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
US5490107A (en) * 1991-12-27 1996-02-06 Fujitsu Limited Nonvolatile semiconductor memory
JP2865469B2 (ja) * 1992-01-24 1999-03-08 三菱電機株式会社 半導体メモリ装置
JPH05303897A (ja) * 1992-04-24 1993-11-16 Matsushita Electric Ind Co Ltd 半導体装置
JP3105092B2 (ja) * 1992-10-06 2000-10-30 株式会社東芝 半導体メモリ装置
TW235363B (enExample) * 1993-01-25 1994-12-01 Hitachi Seisakusyo Kk
US5483486A (en) * 1994-10-19 1996-01-09 Intel Corporation Charge pump circuit for providing multiple output voltages for flash memory
JPH08263361A (ja) * 1995-03-23 1996-10-11 Mitsubishi Electric Corp フラッシュメモリカード
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EP0741387B1 (en) * 1995-05-05 2000-01-12 STMicroelectronics S.r.l. Nonvolatile memory device with sectors of preselectable size and number
JP3153730B2 (ja) * 1995-05-16 2001-04-09 株式会社東芝 不揮発性半導体記憶装置
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US5796657A (en) * 1996-03-29 1998-08-18 Aplus Integrated Circuits, Inc. Flash memory with flexible erasing size from multi-byte to multi-block
US5732030A (en) * 1996-06-25 1998-03-24 Texas Instruments Incorporated Method and system for reduced column redundancy using a dual column select
US5867430A (en) * 1996-12-20 1999-02-02 Advanced Micro Devices Inc Bank architecture for a non-volatile memory enabling simultaneous reading and writing
US5917744A (en) * 1997-12-18 1999-06-29 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines

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