JP2002359254A - Silicon carbide semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent on-resistance of an element from occurring due to dispersion in the channel length increase and the breakdown voltage from decreasing. SOLUTION: A method for manufacturing a silicon carbide semiconductor device comprises the steps of laminating a polysilicon film 21 and an LTO film 22 on a channel layer 5, and then forming openings in the films; steps of implanting an n-type impurity at a predetermined position formed with an n<+> -type source region, through ion implanting with the films as masks and implanting a p-type impurity at a predetermined position formed with a part, in which a highest concentration of the second gate region is obtained; then oxidizing an opening end of a polysilicon film 21 by thermally oxidizing, removing an oxidized part of the film 22 and the film 21, and ion implanting a p-type impurity on the entire area of a predetermined position formed with the second gate region, by ion implanting with a retained part of the film 21 as a mask. Thus, the n<+> -type source region and the second gate region are formed in a self-alignment manner. In this way, dispersion in the channel length can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon carbide (hereinafter referred to as "silicon carbide").
The present invention relates to a semiconductor device (referred to as SiC) and a method of manufacturing the same, and is particularly suitably applied to a J-FET.

[0002]

2. Description of the Related Art FIG. 10 shows an n-channel type J-FE as an example of a SiC semiconductor device used as a power element.
2 shows a cross-sectional configuration of T. As shown in FIG. 10, the n-channel type J-FET is an n ⁺ type substrate J1 made of SiC.
Is formed using a substrate on which an n ⁻ -type epitaxial layer J2 is grown. A p-type first gate region J3 is formed in a surface portion of the n ⁻ -type epi layer J2.

[0003] The first base region J3 and n
^A channel layer J4 is formed on the-type epitaxial layer J2. An n ⁺ -type source region J5 is located in a region of the channel layer J4 located above the first base region J3.
Are formed. Further, n in the first gate region J3
^A p-type second gate region J6 is formed on the surface of the channel layer J4 so as to overlap with a portion extending so as to protrude beyond the ⁺ type source region J5. The first and second gate electrodes J7 and J8 are formed so as to be in contact with the first and second gate regions J3 and J6, and the source electrode J is so as to be in contact with the n ⁺ type source region J5.
9 is formed, and a drain electrode J10 is formed so as to be in contact with the n ⁺ type substrate J1.
T is configured.

[0004]

SUMMARY OF THE INVENTION
The FET forms a channel by controlling the width of a depletion layer extending from the first and second gate regions J3 and J6 toward the channel layer J4, and operates by flowing a current between the source and the drain through the channel. Has become.

In this conventional J-FET, the first and second gate regions J3 and J6 and the n ⁺ -type source region J5 are formed by ion implantation or epitaxial growth. These impurity layers are self-aligned (self-aligned). ), Variations due to mask displacement during fabrication, particularly variations in channel length, occur. For this reason, a problem arises in that a portion having a high on-resistance and a portion having a low on-resistance or a portion having a high withstand voltage and a portion having a low withstand voltage are formed in one cell, thereby increasing the on-resistance of the entire power element and lowering the withstand voltage. Cause a problem.

On the other hand, since SiC has a small diffusion coefficient, the lower end of the conventional first gate region J3 is not sufficiently rounded, and it is difficult to manufacture a body break structure such as a silicon semiconductor. Therefore, breakdown occurs at the two lower ends X of the first gate region J3. In such a case, since the distance from the first gate electrode J7 to the breakdown occurrence site becomes longer, the internal resistance therebetween increases, and as a result, the n ⁺ -type source region J5 located immediately below the source electrode J9 and the second 1 gate region J3 and n ⁻ type epitaxial layer J2 (n ⁺ type substrate J1
) Operates, and the J-FET is destroyed. That is, there is a problem that the avalanche resistance is reduced.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to prevent an increase in on-resistance and a decrease in withstand voltage of an element caused by a variation in channel length. Another object is to prevent the operation of the parasitic bipolar transistor and to ensure avalanche withstand capability.

[0008]

In order to achieve the above object, according to the first aspect of the present invention, the step of forming a source region and the step of forming a second gate region include first and second gate regions formed on a channel layer. A step of arranging the second mask film (21, 22) and forming an opening in a predetermined region of the first and second mask films, and performing ion implantation using the first and second mask films as a mask. By doing so, the first conductivity type impurity is implanted at the position where the source region is to be formed, and the second conductivity type impurity is implanted at the position where the portion of the second gate region located above the source region is to be formed. A step of implanting, a step of performing thermal oxidation in a state where the first mask film is covered with the second mask film, and oxidizing the first mask film from an opening end; a step of forming the second mask film and the first mask After removing the oxidized part of the film, A step of implanting a second conductivity type impurity at a position where a second gate region is to be formed by performing ion implantation using the remaining portion of the first mask film as a mask, and a step of implanting the implanted first and second impurities. Forming a source region and a second gate region by activating the type impurities.

As described above, the first mask film is oxidized while being covered with the second mask film, whereby the first mask film from the opening end is
The oxidation amount of the mask film becomes constant. Therefore, after removing the oxidized portion of the first mask film together with the second mask film, ion implantation is performed using the remaining portion of the first mask film as a mask, so that the source region and the second region are removed. The gate region is formed in a self-aligned manner. For this reason, variations in channel length can be prevented, and an increase in on-resistance and a decrease in withstand voltage of an element caused by the variation in channel length can be prevented.

For example, a polysilicon film can be used as a first mask film as described in claim 2, and an oxide film or a nitride film can be used as a second mask film as described in claim 3. Can be used.

In the invention described in claim 4, the step of forming the source region and the step of forming the second gate region include:
Disposing a mask film (21) on the channel layer;
A step of forming an opening in a predetermined region of the mask film, and ion implantation using the mask film as a mask to implant a first conductivity type impurity at a position where a source region is to be formed, Implanting a second conductivity type impurity at a position where a portion located above the source region in the region is to be formed; and performing isotropic etching on the mask film to form an opening formed in the mask film. Retreating the opening end of the first mask film; and performing ion implantation using the remaining portion of the first mask film as a mask to implant a second conductivity type impurity at a position where the second gate region is to be formed. Forming a source region and a second gate region by activating the implanted first and second conductivity type impurities.

As described above, when the mask film is isotropically etched, the amount of etching at the opening of the mask film becomes constant. Therefore, by performing ion implantation using the remaining portion of the mask film as a mask, the source region is removed. And the second gate region are formed in a self-aligned manner. Therefore, the same effect as the first aspect can be obtained. For example, as described in claim 5, a polysilicon film can be used as the mask film.

According to a sixth aspect of the present invention, a step of forming a first conductivity type body break region (4) below the first gate region is provided. As described above, when the first conductivity type body break region is formed below the first gate region, the electric field can be concentrated on the body break region. For this reason, the breakdown voltage is reduced in the body break region, and the source region and the first
The parasitic bipolar transistor formed by the gate region and the semiconductor layer can be made difficult to operate, and the avalanche withstand capability can be improved. This body break region is formed, for example, by ion implantation using the same mask as the first gate region.

According to the ninth aspect of the present invention, when any one of the first gate region, the source region and the second gate region is formed, an impurity obtained by mixing the first conductivity type impurity and the second conductivity type impurity is used. It is characterized in that it is used. By using such an impurity, activation energy can be reduced, and high-concentration carriers can be formed. Specifically, as set forth in claim 10, the first
When forming the gate region or the second gate region, the concentration of the second conductivity type impurity is higher than that of the first conductivity type impurity, and when forming the source region, the concentration is higher than that of the second conductivity type impurity. The concentration of the first conductivity type impurity is made higher.

When no voltage is applied to the first gate region and the second gate region, a channel is formed by a depletion layer extending from the first gate region and a depletion layer extending from the second gate region. By setting the impurity concentration of the first and second gate regions and the impurity concentration of the channel layer so that the layer is pinched off, the normally-off type silicon carbide semiconductor device can be provided with high safety. For example, as described in claim 12, in the step of forming the channel layer, the channel layer has a lower impurity concentration than the semiconductor layer, whereby the channel layer can be easily made to be a normally-off type.

According to a thirteenth aspect of the present invention, a second conductivity type body break region (4) having a higher concentration than the semiconductor layer is formed under the first gate region. With such a configuration, it is possible to concentrate the electric field in the body break region. For this reason, the breakdown voltage is reduced in the body break region, the operation of the parasitic bipolar transistor including the source region, the first gate region, and the semiconductor layer can be made difficult to operate, and the avalanche withstand capability can be improved.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with specific means described in the embodiments described later.

[0018]

(First Embodiment) FIG. 1 shows a cross-sectional structure of a single gate drive type n-channel J-FET as a silicon carbide semiconductor device according to a first embodiment of the present invention. Hereinafter, the configuration of the J-FET will be described with reference to FIG.

FIG. 1 shows a cross-sectional configuration of one cell of the J-FET. N ⁺ type substrate 1 made of silicon carbide has an upper surface as a main surface and a lower surface opposite to the main surface as a back surface. On the main surface of n ⁺ type substrate 1, n ^{− made of} silicon carbide having a lower dopant concentration than substrate 1 is formed.
The type epi layer 2 is epitaxially grown.

A first gate region 3 made of a p ⁺ -type layer is formed in a predetermined region in a surface portion of the n ⁻ -type epi layer 2. At the end of the first gate region 3, ap ⁻ type region (second conductivity type region) 3a formed so as to have a junction depth deeper than that of the first gate region 3 is formed. This p
^{The −} type region 3 a is formed by thermally diffusing a p-type impurity in the first gate region 3. Further, an n ⁺ type body break region 4 formed in substantially the same pattern as the first gate region 3 is formed below the first gate region 3. The n ⁺ type body break region 4 has a higher concentration (for example, 1 × 10 ¹⁷ to 10 ¹⁸ cm) than the n ⁻ type epi layer 2.
^-3 ), and serves to improve the avalanche resistance as described later.

A channel layer 5 composed of an n ⁻ -type layer is provided on the surface of the n ⁻ -type epi layer 2, including on the first gate region 3.
Are epitaxially grown. An n ⁺ -type source region 6 is formed in a region located above the first gate region 3 in the middle layer portion of the channel layer 5, and the n ⁺ -type source region 6 is formed in the surface layer portion of the channel layer 5. A second gate region 7 made of a p ⁺ -type layer is formed in an upper region. The second gate region 7 has a high concentration as a whole, but has the highest concentration at a portion facing the n ⁺ -type source region 6. Then, the second gate region 7
Is located at a predetermined distance outside the high concentration part,
That is, the junction depth becomes shallow at a position away from the end of the n ⁺ type source region 6 by a predetermined distance. Therefore, the distances S1 and S2 from the end of the n ⁺ type source region 6 to the end of the portion where the junction depth of the second gate region 7 is increased on both the left and right sides of the paper satisfy the relationship of S1 = S2. Has become.

The channel layer 5 penetrates through the second gate region 7 and the n ⁺ -type source region 6 to form the first gate region 3.
Is formed. A source electrode 9 electrically connected to the n ⁺ type source region 6 is formed in the recess 8. In the present embodiment, the first gate region 3 is also electrically connected to the source electrode 9. Configuration. That is, the source electrode 9 is connected to the first gate region 3.
Also serves as a first gate electrode for controlling the potential of the first gate electrode.

The upper part of the second gate region 7 includes
A second gate electrode 10 for controlling the potential of the second gate region 7 is formed. The second gate electrode 10 and the source electrode 9 are in a state of being insulated and separated by a passivation film 11 formed above the source electrode 9 in the recess 8.

Furthermore, on the back side of the n ⁺ -type substrate 1, n ⁺ -type substrate 1 and electrically connected to the drain electrode 12 are formed. As described above, the J-FE in the present embodiment
T is configured.

The J-FET configured as described above is configured to operate in a normally-off type. That is, when no voltage is applied to the second gate electrode 10, the channel layer 5 is pinched off by the depletion layer extending from the first gate region 3 and the depletion layer extending from the second gate region 7. Then, when a desired voltage is applied to the second gate electrode 10, the amount of extension of the depletion layer from the second gate region 7 decreases, a channel is formed, and the source electrode 9 →
n ⁺ type source region 6 → channel layer 5 → n ⁻ type epi layer 2 → n
^A current flows in the order of the ⁺ type substrate 1 → the drain electrode 11.

[0026] In such a J-FET, the ON resistance and breakdown voltage channel length of, i.e. the n ⁺ -type source region 6 from the end portion junction depth is deeper in the second gate region 7 It will be determined by the distance to the end. In contrast, in the present embodiment, as described above,
The distances S1 and S2 from the end of the n ⁺ type source region 6 to the end of the portion where the junction depth of the second gate region 7 is increased are S
Since 1 = S2, the channel length is equal on both left and right sides of the paper. For this reason, it is possible to prevent an increase in the on-resistance and a decrease in the withstand voltage of the element caused by the variation in the channel length.

Further, in the J-FET of this embodiment, since the n ⁺ -type body break region 4 is formed immediately below the first gate region 3, the electric field is concentrated on the n ⁺ -type body break region 4. It becomes possible. For this reason,
According to the structure shown in the present embodiment, the breakdown voltage can be reduced as compared with the conventional case where it is determined at the end of the first gate region J3 (see FIG. 10).
Can be made to break down just below the first gate electrode that plays a role of controlling the potential of the first gate electrode, that is, the source electrode 9. Therefore, it is possible to make it difficult to operate the npn parasitic bipolar transistor including the n ⁺ type source region 6, the first gate region 3, and the n ⁻ type epi layer 2, and to improve the avalanche withstand capability.

Next, a manufacturing process of the J-FET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2A] First, the n-type 4
H, 6H, 3C or 15R-SiC substrate, ie n ⁺
A mold substrate 1 is prepared. For example, the n ⁺ type substrate 1 has a thickness of 400 μm and a main surface of a (0001) Si surface, or
A (112-0) surface is prepared. Then, an n ⁻ -type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface of the substrate 1. In this case, the same crystal as that of the underlying substrate 1 is obtained as the n ⁻ -type epi layer 2, which becomes an n-type 4H, 6H, 3C or 15R-SiC layer.

[0030] the n ^- predetermined region on the type epi layer 2 LTO (L
(Ow Temperature Oxide) film 20 is arranged, and the LTO film 20 is patterned by photolithography to open a predetermined region. Then, ion implantation is performed using the LTO film 20 as a mask. Specifically, first, nitrogen or phosphorus as an n-type impurity is ion-implanted at a position where the n ⁺ -type body break region 4 is to be formed. Subsequently, boron is ion-implanted as a p-type impurity at a position where the first gate region 3 is to be formed. At this time, if necessary, aluminum may be ion-implanted into the surface of the position where the first gate region 3 is to be formed for contact.

[Step shown in FIG. 2 (b)]
Activate the implanted ions. For example, lamp annealing by RTA is performed. As a result, the first gate region 3 is formed, the n ⁺ -type body break region 4 is formed, and the p ⁻ -type region 3 is formed by boron diffusion.
a is formed.

[Step shown in FIG. 3 (a)] After the LTO film 20 is removed, the channel layer including the first gate region 3 is formed on the n ⁻ -type epitaxial layer 2 by epitaxial growth by the n ⁻ -type layer. 5 is formed. At this time, it is preferable that the impurity concentration of the channel layer 5 is lower than that of the n ⁻ -type epi layer 2 in order to make the normally-off type J-FET easier.

[Step shown in FIG. 3B] After a polysilicon film 21 and an LTO film 22 are laminated on the surface of the channel layer 5, the polysilicon film 21 and the LTO film 22 are patterned by photolithography to form a first gate. An opening is formed in the polysilicon film 21 and the LTO film 22 at a portion facing the region 3.

Then, ion implantation is performed using the polysilicon film 21 and the LTO film 22 as a mask. Specifically, first, nitrogen or phosphorus as an n-type impurity is ion-implanted at a position where the n ⁺ -type source region 6 is to be formed. Subsequently, boron or aluminum, which is a p-type impurity, is ion-implanted at a position where a portion having the highest concentration in the second gate region 7 is to be formed.

[Step shown in FIG. 4 (a)]
The polysilicon film 21 is oxidized. At this time, since the LTO film 22 is disposed on the polysilicon film 21,
The polysilicon film 21 is oxidized to a certain amount from the opening end. That is, the polysilicon film 21 is a region into which a p-type impurity or an n-type impurity has been implanted in this step (a position where the n ⁺ -type source region 6 is to be formed or a portion having the highest concentration in the second gate region 7). Is oxidized to a position that is a predetermined distance away from the end of.

[Step shown in FIG. 4B] The oxidized portions of the LTO film 22 and the polysilicon film 21 are removed. Thereby, in the step shown in FIG.
The polysilicon film 21 is opened to the region where the type impurity or the n-type impurity is implanted. Then, the polysilicon film 2
Using 1 as a mask, boron or aluminum as a p-type impurity is ion-implanted. Thereby, the polysilicon film 2
In the opening portion 1, the ion implantation is performed to a deep position, and in the portion where the polysilicon film 21 remains, the ion implantation is performed to a position shallower than the opening portion. That is, a p-type impurity is implanted in the entire region where the second gate region 7 is to be formed.

[Step shown in FIG. 5 (a)] After the polysilicon film 21 is removed, a heat treatment is performed to activate the implanted ions. Thereby, n ⁺ type source region 6
Is formed, and the second gate region 7 is formed.
At this time, as described above, the n ⁺ type source region 6 and the second
Since the position where ions are implanted for forming gate region 7 is determined according to the oxidation amount of polysilicon film 22, n ⁺ -type source region 6 and second gate region 7 are formed.
Are formed by self-alignment (self-alignment).

For this reason, as described above, the distances S1 and S2 from the end of the n ⁺ type source region 6 to the end of the portion where the junction depth of the second gate region 7 is increased have the relationship of S1 = S2. So that

[Step shown in FIG. 5B] After arranging the LTO film 23 on the surface of the second gate region 7, the LTO film 23 is patterned by photolithography to obtain the highest concentration and the highest density in the second gate region 7. The LTO film 23 is opened at a position facing the portion where the LTO film 23 is formed.

[Step shown in FIG. 6 (a)]
By etching using the film 23 as a mask, for example, reactive ion etching (RIE), the second gate region 7 and n
^A concave portion 8 penetrating through the ⁺ type source region 6 and reaching the first gate region 3 is formed.

[Step shown in FIG. 6B] After the passivation film 11 is arranged so as to include the inside of the recess 8, a contact hole is formed by patterning the passivation film 11. And the passivation film 1
After an electrode layer is formed on the first electrode region 1, a source electrode 9 electrically connected to the n ⁺ -type source region 6 and the first gate region 3 is formed by patterning the electrode layer, and the second gate region 7 is formed. Gate electrode 1 electrically connected to
0 is formed. Thereafter, a drain electrode 12 is formed on the back surface side of the n ⁺ type substrate 1, whereby the J−
The FET is completed.

(Second Embodiment) In this embodiment, the J-FET shown in FIG.
Will be described. However, since the outline of the manufacturing process shown in the present embodiment is the same as that of the first embodiment, the same parts are referred to the first embodiment, and only different parts will be described.

First, FIGS. 2A to 2C shown in the first embodiment.
The process is performed up to the step shown in FIG. Then, only the polysilicon film 21 is disposed in the step shown in FIG. 3B, and n-type impurities are implanted into the position where the n ⁺ -type source region 6 is to be formed by ion implantation using only the polysilicon film 21 as a mask. At the same time, a p-type impurity is implanted into the second gate region 7 at a position where the highest concentration portion is to be formed. Thereafter, the steps shown in FIGS. 7A and 7B are performed.

[Step shown in FIG. 7A] The polysilicon film 21 is subjected to isotropic etching, for example, wet etching. As a result, the entire surface of the polysilicon film 21 is etched, the opening end of the opening of the polysilicon film 21 recedes, and the opening end becomes tapered. At this time, the etching amount of the polysilicon film 21 is determined, and the etching amount at the opening end of the polysilicon film 21 is equal (constant) on both left and right sides of the paper.

[Step shown in FIG. 7B] Using the polysilicon film 21 as a mask, boron or aluminum as a p-type impurity is ion-implanted. Thereby, ion implantation is performed to a deep position in the opening portion of the polysilicon film 21, and ion implantation is performed to a position shallower than the opening portion in the portion where the polysilicon film 21 remains. That is, a p-type impurity is implanted in the entire region where the second gate region 7 is to be formed.

Thereafter, FIG. 5A in the first embodiment is used.
By performing the following steps, the same J-FE as in FIG.
T is completed.

Even if the method of isotropically etching the polysilicon film 21 is employed, the amount of etching at the opening of the polysilicon film 21 is fixed, so that the n ⁺ -type source region 6 and the second gate The region 7 is formed by self-alignment (self-alignment). Therefore, the same effect as in the first embodiment can be obtained.

(Third Embodiment) FIG. 8 shows a cross-sectional structure of a J-FET in this embodiment. In the first and second embodiments, the J-FET in which the potential of the first gate region 3 is set to the same potential as that of the n ⁺ type source region 6 by the source electrode 9 is described as an example of the single gate drive type. However, in the present embodiment, the second gate region 7 is set to the same potential as the n ⁺ type source region 6.

That is, as shown in FIG. 8, in the J-FET of this embodiment, the source electrode 31 electrically connected to the n ⁺ type source region 6 is also electrically connected to the second gate region 7. The source electrode 31 serves as a second gate electrode for controlling the potential of the second gate region 7. Further, the first gate electrode 33 electrically connected to the first gate region 3 is electrically separated from the source electrode 31 via the passivation film 32. Regarding other configurations, the J-FET of this embodiment is the same as that of the first embodiment.

The JF of the present embodiment thus configured
The ET is also configured to operate in a normally-off type. That is, when no voltage is applied to first gate electrode 33, channel layer 5 is pinched off by the depletion layer extending from first gate region 3 and the depletion layer extending from second gate region 7. Then, when a desired voltage is applied to the first gate electrode 33, the extension amount of the depletion layer from the first gate region 3 is reduced, and a channel is formed, so that the source electrode 9 → n ⁺ type source region 6 → channel layer The current flows in the order of 5 → n ⁻ type epi layer 2 → n ⁺ type substrate 1 → drain electrode 11.

The J-FET described above can be formed by the same manufacturing method as that of the first embodiment, if the pattern of the electrode layer to be patterned is changed in the manufacturing process of FIG. 6B shown in the first embodiment. You. Also, in such a configuration, since the n ⁺ -type source region 6 and the second gate region 7 are formed in a self-aligned manner, the same effect as in the first embodiment can be obtained. In addition, since the n ⁺ -type body break layer 4 is provided, the avalanche resistance can be improved.

(Fourth Embodiment) FIG. 9 shows a cross-sectional configuration of a J-FET in this embodiment. In the first to third embodiments, the single gate drive type has been described as an example. However, in the present embodiment, the double gate drive type J-type is used.
The FET will be described.

That is, as shown in FIG. 9, the J-FET according to the present embodiment is electrically connected to the source electrode 41 electrically connected to the n ⁺ type source region 6 and the first gate region 3. The second gate electrode 43 electrically connected to the first gate electrode 42 and the second gate region 7 is electrically separated from each other via a passivation film 44. Regarding other configurations, the J-FET of this embodiment is the same as that of the first embodiment.

The JF of the present embodiment thus configured
The ET is also configured to operate in a normally-off type. That is, when no voltage is applied to the first and second gate electrodes 42 and 43, the channel layer 5 is pinched off by the depletion layer extending from the first gate region 3 and the depletion layer extending from the second gate region 7. When a desired voltage is applied to one or both of the first gate electrode 42 and the second gate electrode 43, the amount of extension of the depletion layer from the first and second gate regions 3 and 7 decreases, and a channel is formed. And the source electrode 9 → n ⁺ type source region 6 → channel layer 5
The current flows in the order of → n ⁻ type epi layer 2 → n ⁺ type substrate 1 → drain electrode 11. In such a double-gate drive type J-FET, the amount of extension of the depletion layer can be controlled from both sides of the channel, so that a lower on-resistance can be achieved than in the single-gate drive type.

The J-FET described above can be formed by the same manufacturing method as that of the first embodiment, if the pattern of the electrode layer to be patterned is changed in the manufacturing process of FIG. 6B shown in the first embodiment. You. Also, in such a configuration, since the n ⁺ -type source region 6 and the second gate region 7 are formed in a self-aligned manner, the same effect as in the first embodiment can be obtained. In addition, since the semiconductor device includes the n ⁺ -type body break layer 4, the avalanche withstand capability can be improved.

(Other Embodiments) In the above embodiments, an n-channel type J-FET has been described, but of course, a p-channel type J-FE in which each conductivity type is reversed.
The present invention can be applied to T. In addition, although a normally-off type J-FET has been described as an example, a normally-on type J-FET may be used.

Further, in each of the above embodiments, the case where boron or aluminum is used as the p-type impurity when forming the p-type impurity layer is shown. The activation rate can be improved. Although the case where nitrogen or phosphorus is used as the n-type impurity when forming the n-type impurity layer has been described, both may be used.

Further, a p-type impurity layer (for example, the first and second
In forming the gate regions 3 and 7) and the n-type impurity layer (for example, the n ⁺ -type source region 6), a mixture of a p-type impurity or an n-type impurity may be used as a dopant. In this case, if a p-type impurity layer is formed, the number of p-type impurities is larger than that of an n-type impurity, and if an n-type impurity layer is formed, the number of n-type impurities is larger than that of a p-type impurity. By doing so, the activation energy can be reduced, and a high-concentration carrier can be formed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cross-sectional configuration of a J-FET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the J-FET shown in FIG.

FIG. 3 is a view illustrating a manufacturing step of the J-FET following FIG. 2;

FIG. 4 is a view illustrating a manufacturing step of the J-FET following FIG. 3;

FIG. 5 is a view illustrating a manufacturing step of the J-FET following FIG. 4;

FIG. 6 is a view illustrating a manufacturing step of the J-FET following FIG. 5;

FIG. 7 is a diagram illustrating a manufacturing process of a J-FET according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a cross-sectional configuration of a J-FET according to a third embodiment of the present invention.

FIG. 9 is a diagram illustrating a cross-sectional configuration of a J-FET according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a cross-sectional configuration of a conventional J-FET.

[Explanation of symbols]

1 ... n ⁺ type substrate, 2 ... n ^- type epi layer, 3 ... first gate region, 3a ... p ^- type region, 4 ... n ⁺ type body break region,
5 ... Channel layer, 6 ... n ⁺ -type source region, 7 ... second gate region, 8 ... recess, 9 ... source electrode (first gate electrode), 10 ... second gate electrode, 12 ... drain electrode.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Atsushi Kojima 1-1-1, Showa-cho, Kariya-shi, Aichi F-term in DENSO Corporation (reference) 5F102 FA01 FA02 GB04 GC08 GD04 GJ02 GL04 GR01 HC01 HC07 HC15 HC16 HC21

Claims (14)

[Claims] 1. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than this semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a first gate region (3) of a second conductivity type having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer; and forming a first gate region (3) having a predetermined depth on the semiconductor layer and the first gate region. Forming a one conductivity type channel layer (5); forming a first conductivity type source region (6) at a position in the middle layer of the channel layer facing the first gate region; Forming a second gate region of a second conductivity type so as to include a position facing the source region in a surface layer portion of the channel layer; and forming the second gate region with respect to the channel layer. And the first gate region penetrating the source region. Forming a recess (8) reaching the first gate electrode (9, 33, 42) electrically connected to the first gate region; and a source electrode (9, electrically connected to the source region). 32, 41), a second gate electrode (10, 3) electrically connected to the second gate region.
2, 43), and a step of forming a drain electrode (12) on the back side of the semiconductor substrate, wherein the step of forming the source region comprises: And forming the second gate region, the first and second mask films (21, 2) are formed on the channel layer.
2) arranging and forming an opening in a predetermined region of the first and second mask films; and performing ion implantation using the first and second mask films as a mask, whereby the source is formed. Implanting a first conductivity type impurity at a location where a region is to be formed, and implanting a second conductivity type impurity at a location where a portion of the second gate region located above the source region is to be formed; Thermally oxidizing the first mask film with the second mask film covering the first mask film to oxidize the first mask film from an opening end; and After the oxidized portion of the mask film is removed, ion implantation is performed using the remaining portion of the first mask film as a mask, so that the second gate region is formed at a position where the second gate region is to be formed. Implanting a conductive impurity, Forming the source region and the second gate region by activating the implanted first and second conductivity type impurities. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a polysilicon film is used as said first mask film. 3. The semiconductor device according to claim 1, wherein one of an oxide film and a nitride film is used as said second mask film.
Or the method for manufacturing a silicon carbide semiconductor device according to 2. 4. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a first gate region (3) of a second conductivity type having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer; and forming a first gate region (3) having a predetermined depth on the semiconductor layer and the first gate region. Forming a one conductivity type channel layer (5); forming a first conductivity type source region (6) at a position in the middle layer of the channel layer facing the first gate region; Forming a second gate region of a second conductivity type so as to include a position facing the source region in a surface layer portion of the channel layer; and forming the second gate region with respect to the channel layer. And the first gate region penetrating the source region. Forming a recess (8) reaching the first gate electrode (9, 33, 42) electrically connected to the first gate region; and a source electrode (9, electrically connected to the source region). 32, 41), a second gate electrode (10, 3) electrically connected to the second gate region.
2, 43), and a step of forming a drain electrode (12) on the back side of the semiconductor substrate, wherein the step of forming the source region comprises: And forming the second gate region by disposing a mask film (21) on the channel layer and forming an opening in a predetermined region of the mask film; and using the mask film as a mask. By performing ion implantation,
Injecting a first conductivity type impurity at a position where the source region is to be formed, and implanting a second conductivity type impurity at a position where a portion of the second gate region located above the source region is to be formed. Performing a step of performing isotropic etching on the mask film to recede an opening end of an opening formed in the mask film; and performing ions using a remaining portion of the first mask film as a mask. Implanting a second conductivity type impurity at a position where the second gate region is to be formed by performing the implantation; and activating the implanted first and second conductivity type impurities to form the source region. And a step of forming the second gate region. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein a polysilicon film is used as said mask film. 6. The semiconductor device according to claim 1, further comprising a step of forming a body break region of a first conductivity type under the first gate region. Of manufacturing a silicon carbide semiconductor device. 7. In the step of forming the first gate region and the step of forming the body break region, the first gate region and the body break region are formed by performing ion implantation using the same mask. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein: 8. The step of forming the first gate region, wherein boron is used as a second conductivity type impurity used for the ion implantation, and the first gate region is formed at an end of the first gate region.
8. The silicon carbide semiconductor according to claim 1, further comprising a step of forming the second conductivity type region by diffusing the boron deeper than the gate region. Device manufacturing method. 9. The method according to claim 1, wherein in any one of the step of forming the first gate region, the step of forming the source region, and the step of forming the second gate region, the first gate region, the source region, and the 8. The method according to claim 1, wherein an impurity obtained by mixing an impurity of a first conductivity type and an impurity of a second conductivity type is used when forming one of the two gate regions.
The method for manufacturing a silicon carbide semiconductor device according to any one of the above. 10. The first gate region or the second gate region.
In the case where an impurity obtained by mixing the first conductivity type impurity and the second conductivity type impurity is used for forming a gate region, the concentration of the second conductivity type impurity is higher than that of the first conductivity type impurity. In the case where an impurity obtained by mixing the first conductivity type impurity and the second conductivity type impurity is used for forming the source region,
The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein the concentration of the first conductivity type impurity is higher than that of the second conductivity type impurity. 11. In the step of forming the first gate region, the step of forming the channel layer, and the step of forming the second gate region, a voltage is applied to the first gate region and the second gate region. And when the channel layer is pinched off by the depletion layer extending from the first gate region and the depletion layer extending from the second gate region, the impurity concentration of the first and second gate regions and the channel layer are reduced. 11. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the impurity concentration is set. 12. The step of forming the channel layer,
The method of manufacturing a silicon carbide semiconductor device according to claim 11, wherein the channel layer has a lower impurity concentration than the semiconductor layer. 13. A semiconductor substrate (1) of a first conductivity type made of silicon carbide, and a semiconductor of a first conductivity type formed on a main surface of the semiconductor substrate and made of silicon carbide having a higher resistance than the semiconductor substrate. A layer (2), a first gate region (3) of a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth, and on the semiconductor layer and the first gate region. A first conductivity type channel layer (5) formed, and a first conductivity type source region (6) formed in a middle layer of the channel layer at a position facing the first gate region.
A second gate region of a second conductivity type formed so as to include a position facing the source region in a surface portion of the channel layer; and a second gate region with respect to the channel layer. And a recess (8) formed to penetrate the source region and reach the first gate region; and a first gate electrode (9, 33, 42) electrically connected to the first gate region. A source electrode (9, electrically connected to the source region);
32, 41); a second gate electrode (10, 32, 43) electrically connected to the second gate region; and a drain electrode (1) formed on the back side of the semiconductor substrate.
2), wherein a second conductivity type body break region (4) having a higher concentration than the semiconductor layer is formed below the first gate region. . 14. A portion of the semiconductor layer located at an end of the first gate region, which has a lower concentration than the first gate region and has a deeper junction depth than the first gate region. 14. The silicon carbide semiconductor device according to claim 13, wherein a formed second conductivity type region (3a) is formed.