JP2003068761A - Silicon carbide semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device whose deterioration in the breakdown voltage can be suppressed and the channel resistance can be reduced. SOLUTION: An N<-> -type drift layer 2, a P<+> -type layer 3, and an N<+> -type layer 5 are sequentially formed on an N<+> -type substrate 1 using an epitaxial growth. After a trench 7 reaching the N<-> -type drift layer 2 through the N<+> -type layer 5 and the P<+> -type layer 3 is formed, an N<-> -type channel layer 8 is formed on the internal surface of the trench 7 using an epitaxial growth. Then, a P<+> - type layer 9 is formed by diffusing a P-type impurity into the surface layer of the N<-> -type channel layer 8. The N<-> -type drift layer 2, the P<+> -type layer 3, the N<+> -type layer 5, and the N<-> -type channel layer 8 are formed in self- aligning manner by this manufacture. Also crystal defects in each layer can be eliminated to improve crystallinity. Hereby, deterioration of the breakdown voltage can be suppressed and the channel resistance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device having a J-FET and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 16 shows an N-channel type J-FE as an example of a SiC semiconductor device used as a power element.
The cross-sectional structure of T is shown. As shown in FIG. 16, the N-channel type J-FET is an N ⁺ type substrate J1 made of SiC.
Is formed using the substrate on which the N ⁻ type epi layer J2 is grown. A P type first gate region J3 is formed by ion implantation in the surface layer portion of the N ⁻ type epitaxial layer J2. Then, the channel layer J4 is formed on the N ⁻ type epi layer J2 including the first gate region J3. An N ⁺ type source region J5 is formed in a region located above the first gate region J3 in the channel layer J4.
In addition, the N ⁺ type source region J5 of the first gate region J3
A P-type second gate region J6 formed by epitaxial growth is formed on the surface of the channel layer J4 so as to overlap the portion extended so as to protrude further.
Then, the first and second gate electrodes J7 and J8 are formed so as to be in contact with the first and second gate regions J3 and J6, and the source electrode J9 is formed so as to be in contact with the N ⁺ type source region J5. Further, a drain electrode J10 is formed so as to be in contact with the N ⁺ type substrate J1, and the drain electrode J10 shown in FIG.
ET is configured.

When the J-FET having such a structure is of a normally-off type, the first and second gate electrodes J7 and J8 are used.
The channel layer J4 is designed to be pinched off by the depletion layer extending from the first and second gate regions J3 and J6 toward the channel layer J4 when no voltage is applied to the channel layer J4. Then, the channel is formed by controlling the width of the depletion layer extending from the first and second gate regions J3 and J6, and the J-FET is operated by passing a current between the source and the drain through the channel.

[0004]

In the conventional J-FET, the first and second gate regions J3 and J6 and the N ⁺ type source region J5 are formed by ion implantation or epitaxial growth. Since they are not formed by self-alignment (self-alignment), variations occur due to mask misalignment during fabrication, especially variations in channel length. For this reason, there arises a problem that a portion having a high on-resistance and a portion having a low on-resistance, or a portion having a high breakdown voltage and a portion having a low breakdown voltage are formed in one cell, thereby increasing the on-resistance of the entire power element and lowering the breakdown voltage. Cause the problem.

Further, the above-mentioned conventional normally-off type JF
In ET, the second gate regions J6, N ⁺Mold source area J5
And a parasitic PN formed by the first gate region J3
Prevent the P bipolar transistor from operating
Therefore, the switching operation by each gate is PN
With built-in potential (about 2.9V)
Control is the limit.

However, at present, due to defects or recombination at the PN junction between the first gate region J3 and the channel layer J4 formed by ion implantation, holes are generated from the first gate region J3 and the bipolar transistor operates. Will be lost. Therefore, the above S
It was not possible to use up to the built-in potential (about 2.9 V) of the PN junction which is the theoretical limit of iC. As described above, since the voltages of the first and second gate regions J3 and J6 cannot be increased, the width of the depletion layer extending from the first and second gate regions J3 and J6 cannot be sufficiently reduced, and the channel resistance is reduced. The reduction was not sufficient.

In view of the above points, an object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing a decrease in breakdown voltage and reducing channel resistance, and a method for manufacturing the same.

[0008]

In order to achieve the above object, in the invention described in claim 1, the first conductive type first semiconductor layer (2) and the second conductive type first semiconductor layer (2) are provided on the substrate (1). The second semiconductor layer (3) and the third semiconductor layer (5) of the first conductivity type are epitaxially grown in order, and the third semiconductor layer (5, 3) is penetrated in the cell portion of the semiconductor substrate (6). First
A first trench (7) reaching the semiconductor layer (2);
A first conductivity type channel layer (8) formed on the inner wall surface of the trench (7) by epitaxial growth, a second conductivity type fourth semiconductor layer (9) formed on the channel layer (8), The second semiconductor layer (3) is connected to the first gate region (3
a), the first gate electrode (10) electrically connected to the first gate region (3a) and the fourth semiconductor layer (9) as the second gate region (9a), and the second gate region (9a). ) And a source electrode (12) electrically connected to the source region (5a) using the second gate electrode (11) electrically connected to the source region (5a) as the third semiconductor layer (5). ,
Drain electrode (14) formed on the back surface side of the substrate (1)
It is characterized in that and are provided.

As described above, a semiconductor substrate is used in which a first semiconductor layer of the first conductivity type, a second semiconductor layer of the second conductivity type, and a third semiconductor layer of the first conductivity type are sequentially epitaxially grown on the substrate, and By forming the channel layer on the inner wall surface of the first trench by epitaxial growth, each of these structures can be formed of silicon carbide having good crystallinity without crystal defects. As a result, it is possible to prevent the parasitic bipolar transistor from operating due to a defect or recombination at the PN junction, and it is possible to use up to the built-in potential, so that the channel resistance can be reduced.

Further, in the silicon carbide semiconductor device having such a structure, the first to third semiconductor layers and the channel layer are formed in a self-aligned manner. Therefore, the problem of variation such as mask shift at the time of element formation does not occur, and the variation of channel length does not occur. As a result, the problem that a high ON resistance portion and a low ON resistance portion, or a high breakdown voltage portion and a low breakdown voltage portion are formed in one cell does not occur, but the ON resistance of the entire power element is increased or the breakdown voltage is lowered. It can also be prevented from being brought.

According to the second aspect of the present invention, in the semiconductor substrate (6), the third and second semiconductor layers (5, 3) are formed in the outer peripheral breakdown voltage portion configured to surround the outer periphery of the cell portion. A guard ring is provided, which penetrates and reaches the first semiconductor layer (2). As described above, also in the silicon carbide semiconductor device according to the first aspect, the guard ring can be formed in the outer peripheral breakdown voltage portion.

For example, as described in claim 3, a guard ring is formed so as to penetrate the third and second semiconductor layers (5, 3) to form a first guard ring.
It can consist of a semi-insulating region (16) that extends to the semiconductor layer (2).

A second trench (20) which penetrates the third and second semiconductor layers (5, 3) and reaches the first semiconductor layer (2) through the guard ring. Second
The fifth of the second conductivity type provided on the inner wall of the trench (20)
It can also be configured with a semiconductor layer (9). In this case, as described in claim 5, the guard ring is provided from the inner wall surface of the second trench (20) to the first to third semiconductor layers (2,
(3, 5) extending semi-insulating region (1
It can be configured to include 6).

Further, as described in claim 6, the guard ring penetrates the third and second semiconductor layers (5, 3) to form the first ring.
A second trench (20) reaching the semiconductor layer (2) and a semi-insulating property extended from the inner wall surface of the second trench (20) to the first to third semiconductor layers (2, 3, 5). A structure including the region (16) can also be used.

On the other hand, as described in claim 7, the third and second
The semiconductor layers (5, 3) are removed, and a guard ring (4 made of a first conductivity type semiconductor is formed on the surface layer portion of the first semiconductor layer (2).
1) may be provided.

Further, as described in claim 8, the third and second
The semiconductor layers (5, 3) are removed, and the outer peripheral region (4) made of the first conductivity type semiconductor is formed on the surface layer of the first semiconductor layer (2).
2) may be provided.

The tenth to twenty-first aspects of the present invention relate to a method of manufacturing the silicon carbide semiconductor device according to the first to ninth aspects. Claims 1 to 9 according to these methods
The silicon carbide semiconductor device described in can be manufactured.

According to the eleventh aspect of the present invention, in the step of forming the fourth semiconductor layer (9), the second conductivity type impurity is diffused in the surface layer portion of the channel layer (8) to thereby form the fourth semiconductor layer ( 9) is formed. in this way,
It is possible to form the fourth semiconductor layer by diffusing the second conductivity type impurity in the channel layer 8. By doing so, the crystallinity of the fourth semiconductor layer can be improved, as in the case of forming by epitaxial growth.

The invention as set forth in claim 15 is characterized in that the step of forming the first trench (7) and the step of forming the second trench (20) are performed simultaneously. Thus, it is possible to form the first and second trenches at the same time.

According to the sixteenth aspect of the invention, in the step of forming the channel layer (8), the sixth semiconductor layer (15) of the first conductivity type is formed in the second trench (20) together with the channel layer (8). And forming the fifth semiconductor layer (9), the fifth semiconductor layer (9) is formed by diffusing the second conductivity type impurity into the surface layer portion of the sixth semiconductor layer (15). Is characterized by. In this way, the fifth semiconductor layer forming the guard ring can be formed.

The seventeenth aspect of the invention is characterized in that the step of forming the fourth semiconductor layer (9) and the step of forming the fifth semiconductor layer (9) are performed simultaneously. In this way, the fourth and fifth semiconductor layers can be formed simultaneously.

In the invention described in claim 20, the third and second aspects are provided.
After removing the semiconductor layers (5, 3), a mask material (40) having an opening at a predetermined position is arranged on the surface of the first semiconductor layer (2), and the mask material (40) is protected against silicon carbide from its upper surface. A feature is that the surface layer portion of the first semiconductor layer is made amorphous by implanting active ions, and then the guard ring (41) is formed by diffusing the second conductivity type impurity in the amorphized region. There is.

By thus amorphizing the first semiconductor layer, the second conductivity type impurity can be diffused into the amorphized region. In this way, the guard ring can be formed. Incidentally, claim 21
When forming the outer peripheral region (42) as shown in (4), it is the same as the formation of the guard ring in claim 20.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG. 1 shows a sectional structure of a silicon carbide semiconductor device according to a first embodiment of the present invention. FIG. 1A shows a cross-sectional structure of a J-FET formed in a cell portion of a silicon carbide semiconductor device, and FIG. 1B shows a cross-sectional structure of an outer peripheral breakdown voltage portion. The configuration of the silicon carbide semiconductor device will be described below with reference to FIG.

As shown in FIGS. 1 (a) and 1 (b), silicon carbide
For a semiconductor device, for example, 1 × 10 ¹⁹cm^-3More impure
N as the substance concentration⁺Mold substrate (substrate) 1 and, for example, 1 × 1
0¹⁵~ 5 x 10¹⁶cm^-3N as the impurity concentration of^-Type
The lift layer (first semiconductor layer) 2 and, for example, 1 × 10¹⁸~ 5
× 10¹⁹cm^-3P as the impurity concentration of⁺Mold layer (second half
Conductor layer 3 and, for example, 1 × 10¹⁸~ 5 x 10²⁰cm^-3of
N as impurity concentration ⁺A mold layer (third semiconductor layer) 5 is provided.
It is obtained. These N⁺Mold substrate 1, N^-Type drift layer
2, P⁺Mold layer 3 and N⁺The mold layer 5 is made of silicon carbide.
And the semiconductor substrate 6 is configured by these.
ing.

Further, as shown in FIG. 1 (a), J-FE
On the main surface side of the semiconductor substrate 6 in the T formation region, N ⁺
A trench 7 penetrating the type source region 5 and the P ⁺ type layer 3 and reaching the N ⁻ type drift layer 2 is formed. The inner wall surface of the trench 7 has a thickness of, for example, 1 μm or less, 5 ×
The N ⁻ type channel layer 8 having an impurity concentration of 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ and the P ⁺ type layer having an impurity concentration of 1 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ (fourth semiconductor Layer) 9 is formed in this order.

In the J-FET, the P ⁺ type layers 3 and 9 form the first gate region 3a and the second gate region 9a, and the N ⁺ type layer 5 forms the N ⁺ type source region 5a. On the surfaces of the first and second gate regions 3a and 9a,
For example, Al which is a material capable of ohmic contact with the P ⁺ type layer
And a first gate electrode 10 and a second gate electrode 11 composed of Ni laminated thereon, and N ⁺
A source electrode 12 made of, for example, Ni is formed on the surface of the mold source region 5a. The first and second gate electrodes 10 and 11 and the source electrode 12 are electrically separated via the interlayer insulating film 13.

A drain electrode 14 electrically connected to the N ⁺ type substrate 1 is formed on the back surface side of the semiconductor substrate 6, and the J-FE shown in FIG.
T is configured.

On the other hand, as shown in FIG. 1B, an N ^-- type layer 15 is formed on the surface of the semiconductor substrate 6 in the outer peripheral breakdown voltage portion. The N ⁻ type layer 15 is formed simultaneously with the N ⁻ type channel layer 8 in the J-FET formation region.

A P ⁺ type layer 9 is formed on the surface of the N ⁻ type layer 15. Then, the surface of the P ⁺ -type layer 9, P ⁺ -type layer 9, N ^- -type layer 15, through the N ⁺ -type layer 5 and the P ⁺ -type layer 3, N ^- semi-insulating region reaches the type drift layer 2 16 are formed. The semi-insulating region 16 plays a role as a so-called guard ring, and by extending the electric field extending to the outer periphery breakdown voltage portion to the outer periphery side of the cell portion,
It is designed to relax the electric field.

Then, the interlayer insulating film 13 is formed on the surface of the P ⁺ type layer 9 including the semi-insulating region 16, and the drain electrode 14 is formed on the back surface side of the semiconductor substrate 6, as shown in FIG. An outer pressure resistant portion is configured.

The J-FET thus constructed operates normally off. This operation differs depending on the connection mode of the first and second gate electrodes 10 and 11, and is performed as follows.

First gate electrode 10 and second gate electrode 1
When the potential of the first and second gate electrodes 10 and 11 is independently controllable,
Double gate driving is performed to control the extension amount of the depletion layer extending from both the second gate regions 3a and 9a to the N ⁻ type channel layer 8 side. For example, the first and second gate electrodes 10 and 1
When no voltage is applied to the N ^- type channel layer 8
Is pinched off by the depletion layer extending from both the first and second gate regions 3a and 9a. This makes the source
The current between the drains is turned off. When a forward bias is applied between the first and second gate regions 3a and 9a and the N ⁻ type channel layer 8, the extension amount of the depletion layer extending to the N ⁻ type channel layer 8 is reduced. As a result, the channel region is set and a current flows between the source and the drain.

In the case where only the potential of the first gate electrode 10 can be controlled independently and the potential of the second gate electrode 11 is the same as that of the source electrode 12, the potential of the first gate electrode 10 is set to the same value. Based on this, single gate driving is performed to control the extension amount of the depletion layer extending from the first gate region 3a side to the N ⁻ type channel layer 8 side. In this case also, basically the same operation as in the case of double gate driving is performed, but the channel region is set only by the depletion layer extending from the first gate region 3a side.

In the case where only the potential of the second gate electrode 11 can be controlled independently and the potential of the first gate electrode 10 is the same as that of the source electrode 12, the potential of the second gate electrode 11 is set to the same value. Based on this, single gate drive is performed to control the extension amount of the depletion layer extending from the second gate region 9a side to the N ⁻ type channel layer 8 side. In this case also, basically the same operation as in the case of double gate driving is performed, but the channel region is set only by the depletion layer extending from the second gate region 9a side.

Next, the manufacturing process of the silicon carbide semiconductor device shown in FIG. 1 will be described with reference to the manufacturing process drawings shown in FIGS. 2 to 5, J-F is shown on the left side of the drawing.
The cross-sectional structure of the ET formation region and the stepped structure of the outer peripheral pressure-resistant portion are shown on the right side of the drawing.

[Steps shown in FIGS. 2A and 2B] First,
As shown in FIG. 2A, an N ⁺ type substrate 1 having the above impurity concentration is prepared, and the N ⁻ type drift layer 2, the P ⁺ type layer 3 and the N ⁺ type layer 3 are formed on the surface of the N ⁺ type substrate 1. The semiconductor substrate 6 is formed by sequentially epitaxially growing the mold layer 5. Then, as shown in FIG. 2B, a trench 7 that penetrates the N ⁺ type layer 5 and the P ⁺ type layer 3 and reaches the N ⁻ type drift layer 2 is formed by photolithography in the J-FET formation planned region. Form.

[Steps shown in FIGS. 3A and 3B] FIG.
As shown in (a), the N ⁻ type channel layer 8 and the N ⁻ type layer 15 are epitaxially grown on the surface of the semiconductor substrate 6 including the trench 7. As a result, the N ⁻ type channel layer 8 is formed. At this time, the N ⁻ type drift layer 2 and the P ⁺ type layer 3
And the N ⁺ -type layer 5 are formed by epitaxial growth, and the N ⁻ -type channel layer 8 is epitaxially grown in the trench 7 formed therein, so that the N ⁻ -type drift layer 2, the P ⁺ -type layer 3 and The N ⁺ type layer 5 and the N ⁻ type channel layer 8 are formed in a self-aligned manner.

After that, by performing vapor phase diffusion in an atmosphere of, for example, 1800 to 2000 ° C., P type impurities are diffused in the surface layer portions of the N ⁻ type channel layer 8 and the N ⁻ type layer 15, and FIG. ), A P ⁺ type layer 9 having a predetermined depth is formed. According to this vapor phase diffusion, the P ⁺ type layer 9 can be formed of silicon carbide having good crystallinity without crystal defects, as in the case of epitaxial growth.

[Steps shown in FIGS. 4 (a) and 4 (b)] After a mask having an opening formed in a predetermined region of the outer breakdown voltage region is arranged by photolithography, V ⁺ (vanadium) ion implantation is performed. As a result, as shown in FIG. 4A, the semi-insulating region 16 which functions as a guard ring is formed. Then, selective etching by photolithography is performed to form a contact hole exposing the surface of the N ⁺ type layer 5 in the J-FET formation region as shown in FIG. 4B.

[Step shown in FIG. 5] Selective etching by photolithography is performed to etch a predetermined region of the N ⁺ type layer 5 to expose the surface of the P ⁺ type layer 3.

Although not shown in the subsequent manufacturing process, after forming an interlayer insulating film 13 on the entire surface of the semiconductor substrate 6, a contact hole is formed in the interlayer insulating film 13.
By forming a wiring layer on the interlayer insulating film 13 and patterning the wiring layer, the first and second gate electrodes 10,
11, the source electrode 12 is formed. Then, by forming the drain electrode 14 on the back surface side of the semiconductor substrate 6, as shown in FIG.
The silicon carbide semiconductor device shown in is completed.

As described above, in the silicon carbide semiconductor device according to the present embodiment, the N ^-- type drift layer 2, P ^+.
The type layer 3 and the N ⁺ type layer 5 are formed by epitaxial growth, and the N ⁻ type channel layer 8 is epitaxially grown in the trench 7 formed therein, whereby the N ⁻ type drift layer 2, the P ⁺ type layer 3 and the N ⁺ type layer 3 are formed. The mold layer 5 and the N ⁻ type channel layer 8 are formed in a self-aligned manner. Therefore, the problem of variation such as mask shift at the time of element formation does not occur, and the variation of channel length does not occur. As a result, the problem that a high ON resistance portion and a low ON resistance portion, or a high breakdown voltage portion and a low breakdown voltage portion are formed in one cell does not occur, but the ON resistance of the entire power element is increased or the breakdown voltage is lowered. It can also be prevented from being brought.

Further, in this embodiment, the N ⁻ type channel layer 8 is formed by epitaxial growth, and the P ⁺ type layer 9 is formed in the N ⁻ type channel layer 8 by vapor phase diffusion. Therefore, similarly to the N ⁻ type channel layer 8, the P ⁺ type layer 9 can be made of silicon carbide having no crystal defects and good crystallinity. As a result, it is possible to prevent the parasitic bipolar transistor from operating due to defects or recombination at the PN junction, and it is possible to use up to the built-in potential. Therefore, the depletion layer extending from the first and second gate regions 3a and 9a Width can be shortened enough,
The channel resistance can be reduced.

(Second Embodiment) FIG. 6 shows a sectional structure of a silicon carbide semiconductor device according to a second embodiment of the present invention.
FIG. 6A shows a cross-sectional structure of the J-FET formed in the cell portion of the silicon carbide semiconductor device, and FIG. 6B shows a cross-sectional structure of the outer peripheral breakdown voltage portion. Hereinafter, the configuration of the silicon carbide semiconductor device will be described based on FIG. 6, but since the basic configuration of the silicon carbide semiconductor device in the present embodiment is the same as that in the first embodiment, only different parts will be described.

As shown in FIG. 6B, this embodiment is
A trench 20 is formed in the outer peripheral withstand voltage portion, and the trench 20 is formed.
The P ⁺ type layer (fifth semiconductor layer) 9 and the interlayer insulating film 13 are arranged on the inner wall surface of the first embodiment, which is different from the first embodiment.

Thus, the P ⁺ -type layer 9 is arranged on the inner wall surface of the trench 20, and the P ⁺ -type layer 9 is the N ⁺ -type layer 5 and the P ⁺ -type layer 3.
Even if the structure is such that the N ⁻ -type drift layer 2 is penetrated through to reach the N ⁻ type drift layer 2, the role as a guard ring can be fulfilled similarly to the semi-insulating region 16 in the first embodiment.

7 to 10 show a manufacturing process of the silicon carbide semiconductor device in this embodiment. Hereinafter, a method for manufacturing a silicon carbide semiconductor device will be described with reference to these drawings. 7 to 10, the cross-sectional structure of the J-FET formation region is shown on the left side of the paper surface, and the step surface structure of the outer peripheral withstanding voltage portion is shown on the right side of the paper surface.

[Steps shown in FIGS. 7A and 7B] First,
In the process shown in FIG. 7A, the process shown in FIG.
As in (a), N composed of the above impurity concentration is used.⁺Pattern group
Prepare board 1, N⁺On the surface of the mold substrate 1, N ^-Type drift layer
2, P⁺Mold layer 3 and N⁺Epitaxial growth of the mold layer 5 in order
The semiconductor substrate 6 is formed by increasing the length. After that,
As shown in FIG. 7B, the J-
In the FET formation area, N⁺Mold layer 5 and P⁺Mold layer
3 through N^-The trench 7 reaching the mold drift layer 2
In addition to forming the⁺Mold layer 5 and
And P⁺N through the mold layer 3^-Type reaching the drift layer 2
The punch 20 is formed.

[Steps shown in FIGS. 8A and 8B] FIG.
As shown in (a), the N ⁻ -type channel layer 8 and N ⁻ are formed on the surface of the semiconductor substrate 6 including the trench 7 and the trench 20.
The mold layer (sixth semiconductor layer) 15 is epitaxially grown to a thickness of 1 μm, for example. Then, by photolithography, as shown in FIG. 8 (b), N at the outer withstand voltage portion ^-
The mold layer 15 is selectively etched to reduce the film thickness of the N ⁻ type layer 15 to, for example, about 0.2 μm.

[Steps shown in FIGS. 9A and 9B] For example,
Gas phase diffusion under an atmosphere of 1800-2000 ° C
By doing, N ^-Type surface layer 8 and N^-Mold layer
As shown in FIG. 9A, the P-type impurity is diffused in
P to a predetermined depth⁺The mold layer 9 is formed. By this, N^-
P-type impurities are diffused in the entire region of the mold layer 15 and the entire region is P⁺Type
This is layer 9. After that, the same process as in FIG.
N in the J-FET formation region⁺Expose the surface of the mold layer 5
A contact hole is formed.

[Steps Shown in FIG. 10] The same steps as in FIG. 5 are performed to etch a predetermined region of the N ⁺ -type layer 5 to form the P ⁺ -type layer 3
Expose the surface of.

As described above, the silicon carbide semiconductor device of this embodiment shown in FIG. 6 is completed. Even with this,
The same effect as that of the first embodiment can be obtained, and since it is not necessary to perform the ion implantation for forming the semi-insulating region 16 shown in the first embodiment, the manufacturing process can be simplified. .

(Third Embodiment) This embodiment is the same as the second embodiment.
The process shown in FIG. 11 is added to the embodiment. The step shown in FIG. 11A shows the cross-sectional structure of the outer peripheral breakdown voltage portion when the step shown in FIG. 9A of the second embodiment is performed. After this step, as shown in FIG. 11B, the mask material 3 is formed on the substrate surface.
After 0 is set, V ions are implanted from above the mask material 30. As a result, the semi-insulating region 31 is formed so as to spread from the inner wall surface of the trench 20 to the N ⁺ type layer 5, the P ⁺ type layer 3 and the N ⁻ type drift layer 2 side. After that, FIG.
As shown in (c), the mask material 30 is removed.

Even if the semi-insulating region 31 is further extended from the inner wall surface of the trench 20 as described above,
The guard ring effect as shown in the embodiment can be obtained.

[0057] (Fourth Embodiment) In the above second and third embodiments, N on the inner wall of the trench 20 ^- leaving -type layer 15, N ^- -type layer P ⁺ -type layer by diffusing P-type impurities 15 However, it is not always necessary to leave the N ⁻ -type layer 15 in the structure. In this case, as shown in FIG. 12, after the trench 20 is formed, V is ion-implanted into the inner wall surface of the trench 20 so that the semi-insulating material 31 is extended from the inner wall surface of the trench 20. be able to. Even in this case, the guard ring effect can be obtained by the semi-insulating material 31 as in the third embodiment.

(Fifth Embodiment) In each of the above-described embodiments, the semi-insulating regions 16 and 31 and the trench 20 which are configured to penetrate the N ⁻ type layer 5 and the P ⁺ type layer 3 in the outer peripheral breakdown voltage portion.
However, it is also possible to form a normal guard ring. FIG. 13 shows a cross-sectional structure during the manufacturing process of the silicon carbide semiconductor device according to the present embodiment, which will be described with reference to this drawing. However, regarding the same parts as those of the first embodiment in the manufacturing process of the silicon carbide semiconductor device,
A description will be given with reference to the exemplary embodiment.

First, FIGS. 2A to 2C in the first embodiment.
After performing the steps shown in FIG. 3B, the steps shown in FIG.
The step shown in FIG. 4B is performed without performing the step. That
Then, the process shown in FIG. 5 is performed. At this time,
Then, without covering with a mask, N ^-The mold layer 5 is completely removed
So that Then, the outer pressure resistant portion is exposed, and the cell portion is exposed.
After placing a mask that covers the
P of the withstand voltage part⁺The mold layer 3 is removed. As a result,
N in the pressure section^-Mold layer 5 and P⁺Form layer 3 removed
It becomes a state.

Then, as shown in FIG. 13, a mask 40 of carbon resist or the like is formed on the surface of the N ⁻ type drift layer 2 so that a guard ring formation planned position is opened.
By implanting inactive ions such as r and C into SiC, a predetermined position of the N ⁻ type drift layer 2 is made amorphous. Then, P-type impurities are vapor-phase-diffused using the mask 40 used as it is, thereby forming P ⁺ -type layers 41a at equal intervals in the surface layer portion of the N ⁻ -type drift layer 2.
As a result, the guard ring 41 including the plurality of P ⁺ type layers 30a is formed.

As described above, with respect to the outer peripheral breakdown voltage portion, even if the N ⁻ type layer 5 and the P ⁺ type layer 3 are removed and the guard ring 41 is formed on the surface layer portion of the N ⁻ type drift layer 2, the first
The same effect as the embodiment can be obtained.

In forming the guard ring 41, the depth at which the P-type impurities are diffused depends on the depth of the amorphized region, and therefore the guard ring 41 is guarded by the depth at which the inactive ions are implanted. It is possible to control the depth of the ring 41.

(Sixth Embodiment) Instead of the guard ring 41 shown in the fifth embodiment, or together with the guard ring 41, the outer peripheral P-type region can be formed. In Figure 14,
A cross-sectional structure of the silicon carbide semiconductor device according to the present embodiment during the manufacturing process is shown, and a description will be given based on this drawing. However, description of the same steps as those of the fifth embodiment in the manufacturing process of the silicon carbide semiconductor device will be omitted.

First, similarly to the fifth embodiment, the N ⁻ type layer 5 and the P ⁺ type layer 3 in the outer peripheral breakdown voltage portion are removed. After that, as shown in FIG. 14, a mask 40 such as a carbon resist having an opening at the outer peripheral P-type region formation planned position is arranged, and then an inert ion is implanted into SiC such as Ar or C. A predetermined position of the N ⁻ type drift layer 2 is made amorphous. After that, the mask 40 used previously is used as it is to diffuse the P-type impurities in the vapor phase, and thereby N ⁻
An outer peripheral P-type region 42 is formed in the surface layer portion of the mold drift layer 2.

As described above, with respect to the outer peripheral breakdown voltage portion, the N ⁻ type layer 5 and the P ⁺ type layer 3 are removed and the outer peripheral P type region 42 is formed in the surface layer portion of the N ⁻ type drift layer 2. The same effect as the first embodiment can be obtained. The depth of the outer peripheral P-type region 42 also depends on the depth of the amorphized region, and can be controlled by the depth at which inert ions are implanted.

(Seventh Embodiment) The configuration of the outer peripheral P-type region 42 shown in the sixth embodiment can be changed.
FIG. 15 shows a cross-sectional structure during the manufacturing process of the silicon carbide semiconductor device according to the present embodiment, which will be described with reference to this drawing. However, the sixth step in the manufacturing process of the silicon carbide semiconductor device
The description of the same parts as those in the embodiment will be omitted.

First, similarly to the sixth embodiment, the N ⁻ type layer 5 and the P ⁺ type layer 3 in the outer peripheral breakdown voltage portion are removed. After that, a mask such as carbon resist having an opening on the inner peripheral side of the planned outer peripheral P-type region formation position is arranged, and then Ar
By implanting inactive ions into SiC such as C and C, a predetermined position of the N ⁻ type drift layer 2 is made amorphous. After that, using the mask used previously as it is, P
Al is vapor-phase diffused as a type impurity. As a result, the inner peripheral region 42a of the outer peripheral P-type region 42 is formed.

Subsequently, a mask of carbon resist or the like having an opening on the outer peripheral side of the planned outer peripheral P-type region formation position is arranged, and then inert ions are implanted into SiC such as Ar or C. A predetermined position of the N ⁻ type drift layer 2 is made amorphous. After that, B is vapor-phase diffused as a P-type impurity using the mask used as it is.
As a result, the outer peripheral side region 4 of the outer peripheral portion P-type region 42
2b is formed. At this time, since B is more likely to diffuse than Al, the outer peripheral region 42b is inner peripheral region 4
2a and the outer peripheral region 4
In 2b, graduation occurs in which the impurity concentration gradually decreases from the shallow position to the deep position.

As described above, the outer peripheral portion P-type region 42 is constituted by the inner peripheral portion region 42a and the outer peripheral portion region 42b, and the outer peripheral portion region 42b is deeper than the inner peripheral portion region 42a, and is located from a shallow position to a deep position. It is also possible to adopt a configuration having a graduation in which the impurity concentration gradually decreases over time. With such a structure, the breakdown voltage of the silicon carbide semiconductor device can be improved.

(Other Embodiments) In each of the above embodiments, the silicon carbide semiconductor device including the J-FET having the N ⁻ type channel layer 8 as the channel is described. J-FET in which a P-type impurity layer in which the conductivity type of each component of the device is inverted serves as a channel
The present invention can be applied to a silicon carbide semiconductor device provided with.

In the above embodiment, the normally-off type J-FET has been described as an example, but the present invention is not limited to the normally-off type J-FET, and can be applied to the normally-on type J-FET. In this case, for example, the impurity concentration of the N− type channel layer 8 can be set to about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG.

FIG. 3 is a diagram showing a manufacturing process of the silicon carbide semiconductor device, following FIG. 2.

FIG. 4 is a diagram showing a manufacturing process of the silicon carbide semiconductor device, following FIG. 3.

FIG. 5 is a diagram showing a manufacturing process of the silicon carbide semiconductor device, following FIG.

FIG. 6 is a diagram showing a cross-sectional structure of a silicon carbide semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 6.

FIG. 8 is a diagram showing the manufacturing process of the silicon carbide semiconductor device, following FIG. 7.

FIG. 9 is a diagram showing a manufacturing process of the silicon carbide semiconductor device, following FIG. 8.

FIG. 10 is a diagram showing a manufacturing process of the silicon carbide semiconductor device, following FIG. 9.

FIG. 11 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the third embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the fourth embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the fifth embodiment of the present invention.

FIG. 14 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the sixth embodiment of the present invention.

FIG. 15 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the second embodiment of the present invention.

FIG. 16 is a diagram showing a cross-sectional structure of a conventional silicon carbide semiconductor device.

[Explanation of symbols]

1 ... N ⁺ type substrate, 2 ... N ⁻ type drift layer, 3 ... P ⁺ type layer,
3a ... first gate region, 5 ... N ⁺ -type layer, 5a ... N ⁺ -type source region, 6 ... semiconductor substrate, 7 ... trench, 8 ... N ^- -type channel layer, 9 ... P ⁺ -type layer, 9a ... second Gate area, 10
... 1st gate electrode, 11 ... 2nd gate electrode, 12 ... Source electrode, 14 ... Drain electrode.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tsuyoshi Yamamoto             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO F-term (reference) 5F102 FA01 FA02 GA14 GB05 GC08                       GD04 GJ02 GR04 GR07 HC01                       HC05 HC07 HC15

Claims (22)

[Claims] 1. A substrate (1) made of silicon carbide of a first conductivity type, and a first conductivity type first substrate formed by epitaxial growth on the substrate (1) and having a concentration lower than that of the substrate (1). 1 semiconductor layer (2), a second conductive type second semiconductor layer (3) formed on the first semiconductor layer (2) by epitaxial growth, and formed on the second semiconductor layer (3) by epitaxial growth A semiconductor substrate (6) provided with a third semiconductor layer (5) of the first conductivity type, wherein in the cell portion of the semiconductor substrate (6), the third and second semiconductor layers (5, 3) through the first
A first trench (7) reaching the semiconductor layer (2); a first conductivity type channel layer (8) formed by epitaxial growth on an inner wall surface of the first trench (7); A second conductive type fourth semiconductor layer (9) formed above and the second semiconductor layer (3) are used as a first gate region (3a) and electrically connected to the first gate region (3a). And a second gate electrode (11) electrically connected to the second gate region (9a) and the fourth semiconductor layer (9) as a second gate region (9a). And a source electrode (12) electrically connected to the source region (5a) with the third semiconductor layer (5) as a source region (5a), and formed on the back surface side of the substrate (1). Drain electrode (1
4) The silicon carbide semiconductor device is provided with. 2. In the semiconductor substrate (6), an outer peripheral breakdown voltage portion configured to surround the outer periphery of the cell portion penetrates the third and second semiconductor layers (5, 3) and First
The silicon carbide semiconductor device according to claim 1, further comprising a guard ring that reaches the semiconductor layer (2). 3. The guard ring is composed of a semi-insulating region (16) which penetrates the third and second semiconductor layers (5, 3) and reaches the first semiconductor layer (2). The silicon carbide semiconductor device according to claim 2. 4. The second trench (20), wherein the guard ring penetrates the third and second semiconductor layers (5, 3) and reaches the first semiconductor layer (2), and the second trench (20). Two
3. The silicon carbide semiconductor device according to claim 2, wherein the silicon carbide semiconductor device is configured to have a second conductivity type fifth semiconductor layer (9) provided on the inner wall of (0). 5. The guard ring extends from the inner wall surface of the second trench (20) to the first to third semiconductor layers (2,
(3, 5) extending semi-insulating region (1
6. It is comprised including 6), It is characterized by the above-mentioned.
The silicon carbide semiconductor device according to. 6. The guard ring includes a second trench (20) penetrating the third and second semiconductor layers (5, 3) to reach the first semiconductor layer (2), and a second trench (20). 20) from the inner wall surface of the first to third semiconductor layers (2,
(3, 5) extending semi-insulating region (1
6. It is constituted by including 6).
The silicon carbide semiconductor device according to. 7. The third and second semiconductor layers (5, 3) are removed in an outer peripheral breakdown voltage portion of the semiconductor substrate (6) surrounding the outer periphery of the cell portion. The silicon carbide semiconductor device according to claim 1, further comprising a guard ring (41) made of a first conductivity type semiconductor provided on a surface layer portion of the first semiconductor layer (2). 8. The third and second semiconductor layers (5, 3) are removed in the outer periphery breakdown voltage portion of the semiconductor substrate (6) surrounding the outer periphery of the cell portion. The silicon carbide semiconductor device according to claim 1, further comprising an outer peripheral region (42) formed of a first conductivity type semiconductor in a surface layer portion of the first semiconductor layer (2). 9. The outer peripheral side portion (42b) of the outer peripheral portion region (42) is deeper than the inner peripheral side portion (42a), and the outer peripheral side portion (42b) is deeper. 9. The silicon carbide semiconductor device according to claim 8, wherein the silicon carbide semiconductor device has a graduation in which the impurity concentration is gradually reduced from a shallow position to a deep position. 10. A first conductivity type first semiconductor layer (2) having a lower concentration than that of the substrate (1) and a second conductivity type substrate (1) made of silicon carbide of the first conductivity type. By epitaxially growing the second semiconductor layer (3) and the third semiconductor layer (5) of the first conductivity type in this order, the substrate (1) and the first semiconductor layer (5) are formed.
~ A step of forming a semiconductor substrate (6) having a third semiconductor layer (2, 3, 5); and in the cell part of the semiconductor substrate (6),
The first semiconductor layer (2) penetrating the semiconductor layers (5, 3)
Forming a first trench (7) reaching the first trench (7), forming a first conductivity type channel layer (8) on the inner wall surface of the first trench (7) by epitaxial growth, and forming the channel layer (8) Forming a second conductive type fourth semiconductor layer (9) thereon; and forming the second semiconductor layer (3) as a first gate region (3a) and electrically connecting to the first gate region (3a). Forming a first gate electrode (10) to be connected, and making the fourth semiconductor layer (9) a second gate region (9a), and electrically connecting to the second gate region (9a) 2 a step of forming a gate electrode (11), and a step of forming a source electrode (12) electrically connected to the source region (5a) by using the third semiconductor layer (5) as a source region (5a) On the back surface side of the substrate (1), the drain electrode (1 The method of manufacturing a silicon carbide semiconductor device, characterized by a step of forming a). 11. The step of forming the fourth semiconductor layer (9) forms the fourth semiconductor layer (9) by diffusing a second conductivity type impurity into a surface layer portion of the channel layer (8). The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein: 12. In the semiconductor substrate (6), in an outer peripheral breakdown voltage portion configured so as to surround the outer periphery of the cell portion, the third and second semiconductor layers (5, 3) are penetrated to the outer peripheral breakdown voltage portion. First
The method for manufacturing a silicon carbide semiconductor device according to claim 11, further comprising a step of forming a guard ring that reaches the semiconductor layer (2). 13. In the step of forming the guard ring, a semi-insulating impurity is ion-implanted so as to penetrate the third and second semiconductor layers (5, 3) and reach the first semiconductor layer (2). 13. A semi-insulating region (16) is formed as the guard ring by doing so.
A method of manufacturing a silicon carbide semiconductor device according to item 1. 14. In the step of forming the guard ring, a second trench (20) which penetrates the third and second semiconductor layers (5, 3) and reaches the first semiconductor layer (2) is formed. The method for manufacturing a silicon carbide semiconductor device according to claim 12, wherein a fifth conductivity type fifth semiconductor layer (9) is then formed on the inner wall surface of the second trench. 15. The method of manufacturing a silicon carbide semiconductor device according to claim 14, wherein the step of forming the first trench (7) and the step of forming the second trench (20) are performed at the same time. . 16. In the step of forming the channel layer (8), a sixth-conductivity-type sixth semiconductor layer (15) is formed in the second trench (20) together with the channel layer (8), In the step of forming the fifth semiconductor layer (9), the fifth semiconductor layer (9) is formed by diffusing a second conductivity type impurity into a surface layer portion of the sixth semiconductor layer (15). 16. The method for manufacturing a silicon carbide semiconductor device according to claim 14 or 15. 17. The silicon carbide semiconductor device according to claim 15, wherein the step of forming the fourth semiconductor layer (9) and the step of forming the fifth semiconductor layer (9) are performed at the same time. Production method. 18. The step of forming the guard ring comprises forming the second trench (20) and then forming the second trench (20).
By implanting semi-insulating impurities into the inner wall surface of the trench (20), the semi-insulating property spreading from the inner wall surface of the second trench (20) to the first to third semiconductor layers (2, 3, 5). The method for manufacturing a silicon carbide semiconductor device according to claim 14, wherein the region (16) is formed. 19. In the step of forming the guard ring, a second trench (20) is formed which penetrates the third and second semiconductor layers (5, 3) and reaches the first semiconductor layer (2). After that, by ion-implanting a semi-insulating impurity into the inner wall surface of the second trench (20), the first to third semiconductor layers (2, 2) are formed from the inner wall surface of the second trench (20).
The method for manufacturing a silicon carbide semiconductor device according to claim 12, wherein a semi-insulating region (16) extending over 3, 5) is formed. 20. In the semiconductor substrate (6), in the outer peripheral breakdown voltage portion configured to surround the outer periphery of the cell portion, after removing the third and second semiconductor layers (5, 3), A mask material (40) having an opening at a predetermined position is arranged on the surface of the first semiconductor layer (2), and ions inert to silicon carbide are implanted from the upper surface of the mask material (40). 1 Amorphize the surface layer of the semiconductor layer, then
The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein a guard ring (41) is formed by diffusing a second conductivity type impurity in the amorphized region. 21. In the outer periphery breakdown voltage portion of the semiconductor substrate (6) surrounding the outer periphery of the cell portion, after removing the third and second semiconductor layers (5, 3), A mask material (40) having an opening at a predetermined position is arranged on the surface of the first semiconductor layer (2), and ions inert to silicon carbide are implanted from the upper surface of the mask material (40). 1 Amorphize the surface layer of the semiconductor layer, then
The method for manufacturing a silicon carbide semiconductor device according to claim 10 or 11, wherein an outer peripheral region (42) is formed by diffusing a second conductivity type impurity in the amorphized region. 22. In the step of forming the outer peripheral area (42), an inner peripheral side portion (42) of the outer peripheral area (42) is formed.
As compared with a), the outer peripheral side portion (42b) has a deeper depth, and the outer peripheral side portion (42b) has a graduation in which the impurity concentration is gradually reduced from the shallow position to the deeper position. The method of manufacturing a silicon carbide semiconductor device according to claim 21, wherein the outer peripheral region (42) is formed.