JPH06112216A - High breakdown strength semiconductor device - Google Patents
High breakdown strength semiconductor deviceInfo
- Publication number
- JPH06112216A JPH06112216A JP25658692A JP25658692A JPH06112216A JP H06112216 A JPH06112216 A JP H06112216A JP 25658692 A JP25658692 A JP 25658692A JP 25658692 A JP25658692 A JP 25658692A JP H06112216 A JPH06112216 A JP H06112216A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- junction
- electrode
- high breakdown
- breakdown voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 230000015556 catabolic process Effects 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 description 18
- 239000007769 metal material Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000002040 relaxant effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高耐圧半導体装置に係
り、特に接合終端部に十分なｐｎ接合が無い高耐圧半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a high breakdown voltage semiconductor device in which a junction termination portion does not have a sufficient pn junction.
【０００２】[0002]
【従来の技術】パワー素子は、電流増幅，電源装置，電
動制御などに使われ、高耐圧で大電流動作を目的とした
構造設計がなされる。2. Description of the Related Art A power element is used for current amplification, a power supply device, electric control, etc., and has a structural design designed for high withstand voltage and large current operation.
【０００３】高耐圧化のためには、例えば、バイポーラ
トランジスタの場合、コレクタ低不純物濃度層を厚く高
抵抗にして降状電圧を上げ、ベース層を大きくとってパ
ンチパンチスールーを防ぐ手法がある。しかし、この種
の手法は大電流化や高速化と相反するので、トランジス
タの使用目的に応じた最適のトレードオフ設計がなされ
る。In order to increase the breakdown voltage, for example, in the case of a bipolar transistor, there is a method in which a collector low impurity concentration layer is thickened to have high resistance to increase the breakdown voltage and a large base layer is used to prevent punch punch sulu. However, since this kind of method conflicts with a large current and a high speed, an optimum trade-off design is made according to the purpose of use of the transistor.
【０００４】また、高耐圧化のためには、従来より、フ
ィールドプレートやガードリングなどの手法が用いられ
ている。In order to increase the breakdown voltage, methods such as field plates and guard rings have been conventionally used.
【０００５】フィールドプレートは、図９（ａ）に示す
ように、ベース電極８１をｎ型コレクタ層８２の上部８
３まで引き出すことにより、空乏層８４をｎ型コレクタ
層８２の上部８３まで延ばし、ｐ型ベース層８５とｎ型
コレクタ層８２とのｐｎ接合部分、つまり、接合終端部
の空乏層電界を緩和し、電界集中を防止する。なお、図
中、８６はｎ型エミッタ層，８７は酸化膜を示してい
る。In the field plate, as shown in FIG. 9A, the base electrode 81 is formed on the upper portion 8 of the n-type collector layer 82.
By pulling up to 3, the depletion layer 84 is extended to the upper portion 83 of the n-type collector layer 82, and the depletion layer electric field at the pn junction between the p-type base layer 85 and the n-type collector layer 82, that is, the junction termination portion is relaxed. , Prevent electric field concentration. In the figure, 86 is an n-type emitter layer and 87 is an oxide film.
【０００６】ガードリングは、図９（ｂ）に示すよう
に、ｐ型ベース層８５を囲んで１ないし数個のフローテ
ィングガードリング８８を設けることにより、接合終端
部の空乏層電界を緩和する。As shown in FIG. 9B, the guard ring is provided with one or several floating guard rings 88 surrounding the p-type base layer 85 to relax the electric field of the depletion layer at the junction termination portion.
【０００７】しかしながら、このような高耐圧化の手法
には次のような問題がある。However, such a method of increasing the breakdown voltage has the following problems.
【０００８】即ち、素子の主接合がｐｎ接合ではないパ
ワー素子、例えば、ショットキーバリアダイオード，Ｕ
−ＭＯＳ，埋込みゲート構造ＭＯＳサイリスタ，埋込み
ゲート構造ＩＧＢＴなどの接合終端部は高耐圧化に必要
な十分なｐｎ接合を素子の主な工程とは別に作る必要が
ある。また、Ｓｉなどのように不純物拡散が比較的容易
な材料からなる基板の場合には、素子部とは別にｐｎ接
合を形成するのは可能であるが、ＳｉＣなどの化合物半
導体や、ダイヤモンドのように不純物拡散が困難な材料
からなる基板の場合には、従来のｐｎ接合を前提とした
高耐圧化の手法は使用が困難である。That is, a power element whose main junction is not a pn junction, such as a Schottky barrier diode, U
In a junction termination portion such as -MOS, buried gate structure MOS thyristor, buried gate structure IGBT, etc., it is necessary to form a sufficient pn junction required for high breakdown voltage separately from the main process of the device. Further, in the case of a substrate made of a material such as Si which is relatively easy to diffuse impurities, it is possible to form a pn junction separately from the element portion, but a compound semiconductor such as SiC or diamond. In the case of a substrate made of a material in which impurity diffusion is difficult, it is difficult to use the conventional method of increasing the breakdown voltage based on the pn junction.
【０００９】[0009]
【発明が解決しようとする課題】上述の如く、従来の半
導体パワー素子の高耐圧化の手法は、接合終端部がｐｎ
接合の場合を前提にしたものであった。このため、接合
終端部に十分なｐｎ接合が無く、拡散係数が小さい基板
の場合には、半導体パワー素子の高耐圧化が困難である
という問題があった。As described above, in the conventional method for increasing the withstand voltage of the semiconductor power element, the junction termination portion is pn.
It was based on the case of joining. Therefore, there is a problem that it is difficult to increase the breakdown voltage of the semiconductor power element in the case of a substrate having a small diffusion coefficient without a sufficient pn junction at the junction termination portion.
【００１０】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、接合終端部に十分なｐ
ｎ接合が無い場合でも、高耐圧を実現できる構造の高耐
圧半導体装置を提供することにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a sufficient p
It is an object of the present invention to provide a high breakdown voltage semiconductor device having a structure capable of realizing a high breakdown voltage even when there is no n-junction.
【００１１】[0011]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の高耐圧半導体装置は、半導体基板に形成
された素子の主電流が流れる領域と、前記主電流の流れ
る領域を囲むように形成され、前記主電流の流れる領域
を囲むように形成され、且つ前記主電流が流れる電極と
電気的に分離された溝を内部に有する接合終端領域とを
備えたことを特徴とする。In order to achieve the above object, a high breakdown voltage semiconductor device of the present invention surrounds a region in which a main current of an element formed on a semiconductor substrate flows and a region in which the main current flows. And a junction terminating region having a groove inside which is formed so as to surround the region in which the main current flows and which is electrically isolated from the electrode in which the main current flows.
【００１２】なお、接合終端領域とは、素子の主電流が
流れる領域以外の領域であって、耐圧を大きくするため
の構造を有する領域である。The junction termination region is a region other than the region through which the main current of the element flows, and has a structure for increasing the breakdown voltage.
【００１３】[0013]
【作用】本発明によれば、接合終端領域内に設けられ
た、主電流が流れる電極と電気的に分離された溝により
接合終端部の空乏層電界の集中が緩和される。このた
め、接合終端部にｐｎ接合が無くても、高耐圧化でき
る。According to the present invention, the concentration of the depletion layer electric field at the junction termination portion is relaxed by the groove provided in the junction termination region and electrically isolated from the electrode through which the main current flows. Therefore, even if there is no pn junction at the junction termination portion, high breakdown voltage can be achieved.
【００１４】[0014]
【実施例】以下、図面を参照しながら実施例を説明す
る。Embodiments will be described below with reference to the drawings.
【００１５】図１は、本発明の第１の実施例に係る高耐
圧半導体装置の平面図である。FIG. 1 is a plan view of a high breakdown voltage semiconductor device according to the first embodiment of the present invention.
【００１６】図中、１は素子の主電流が流れる領域を示
しており、この主電流領域１の回りの領域３は接合終端
領域を示している。接合終端領域３の内部には、複数の
リング状の溝２が主電流領域１と同心的に形成されてい
る。なお、溝の数は、必要な耐圧等に応じて決まるもの
で１個の場合もある。In the figure, 1 indicates a region where the main current of the device flows, and region 3 around the main current region 1 indicates a junction termination region. Inside the junction termination region 3, a plurality of ring-shaped grooves 2 are formed concentrically with the main current region 1. The number of grooves is determined depending on the required breakdown voltage and the like, and may be one.
【００１７】図２は、図１の一点鎖線で囲まれた領域の
より詳しい図であり、図２（ａ）は平面図、図２（ｂ）
は図２（ａ）のＡ−Ａ´断面図である。FIG. 2 is a more detailed view of the area surrounded by the alternate long and short dash line in FIG. 1, FIG. 2 (a) being a plan view and FIG. 2 (b).
FIG. 3 is a sectional view taken along the line AA ′ of FIG.
【００１８】図中、１０は低濃度のｎ型ＳｉＣ基板を示
しており、このｎ型ＳｉＣ基板１０の主電流領域１の表
面には、内面がＳｉＯ2 膜５で被覆された溝４が形成さ
れている。なお、２つの溝４の間のｎ型ＳｉＣ基板の表
面には、ＳｉＯ2 膜５は形成されていない。そして、溝
４の内部は金属材料で充填され、２つの溝４はこの金属
材料で繋がっている。In the figure, 10 indicates a low-concentration n-type SiC substrate. On the surface of the main current region 1 of this n-type SiC substrate 10, a groove 4 whose inner surface is covered with a SiO 2 film 5 is formed. Has been done. The SiO 2 film 5 is not formed on the surface of the n-type SiC substrate between the two grooves 4. The inside of the groove 4 is filled with a metal material, and the two grooves 4 are connected by this metal material.
【００１９】即ち、金属材料が充填された２つの溝４の
中に形成された電極に接してアノード電極６が形成さ
れ、そして、このアノード電極６とｎ型ＳｉＣ基板１０
とのショットキー接合により、ショットキーバリアダイ
オードが形成されている。このショットキーバリアダイ
オードの主電流が流れる電極はアノード電極６である。That is, the anode electrode 6 is formed in contact with the electrodes formed in the two grooves 4 filled with the metal material, and the anode electrode 6 and the n-type SiC substrate 10 are formed.
A Schottky barrier diode is formed by the Schottky junction with and. The electrode through which the main current of this Schottky barrier diode flows is the anode electrode 6.
【００２０】一方、接合終端領域３の溝２も同様にその
内面がＳｉＯ2 膜５で被覆され、その内部が金属材料で
充填され、２つの溝２が金属材料で繋がっている。On the other hand, similarly, the groove 2 of the junction termination region 3 has its inner surface covered with the SiO 2 film 5, the inside thereof is filled with a metal material, and the two grooves 2 are connected by the metal material.
【００２１】即ち、２つの溝２ごとに電位の浮いた電極
７が１つ形成されている。That is, one electrode 7 having a floating potential is formed for each of the two grooves 2.
【００２２】また、ｎ型ＳｉＣ基板１０の裏面には、高
濃度のｎ型半導体膜からなるコンタクト層８を介してカ
ソード電極９が設けられている。このカソード電極９に
は主電流は流れない。A cathode electrode 9 is provided on the back surface of the n-type SiC substrate 10 via a contact layer 8 made of a high-concentration n-type semiconductor film. No main current flows through this cathode electrode 9.
【００２３】このようなショットキーバリアダイオード
からなる高耐圧半導体装置に高電圧の逆バイアス電圧が
印加されると、ｎ型ＳｉＣ基板１０内に大きい空乏層が
形成され、高電界が生じる。When a high reverse bias voltage is applied to the high breakdown voltage semiconductor device composed of such a Schottky barrier diode, a large depletion layer is formed in the n-type SiC substrate 10 and a high electric field is generated.
【００２４】ここで、溝２が無いと各電位の電気力線が
全てアノード電極６の端部下部１１に集中し、素子が破
壊される。If the groove 2 is not provided, the lines of electric force of each potential are concentrated on the lower portion 11 of the end portion of the anode electrode 6 and the element is destroyed.
【００２５】一方、本実施例のように、溝２を設ける
と、各１対の溝ごとに等電位の電気力線が集まり、そし
て、アノード電極１１から遠い１対の溝ほど高い電位の
電気力線が集まる。この結果、基板表面の電界強度が小
さくなり、素子の破壊を防止できる。On the other hand, when the groove 2 is provided as in this embodiment, lines of electric force of equal potential are gathered in each pair of grooves, and the electric potential of the pair of grooves farther from the anode electrode 11 is higher. The lines of force gather. As a result, the electric field strength on the surface of the substrate is reduced, and the element can be prevented from being destroyed.
【００２６】かくして本実施例によれば、ＳｉＣのよう
に不純物拡散が難しい材料からなる半導体基板を用い、
接合終端部にｐｎ接合が無い場合でも、接合終端領域３
に形成され、アノード電極１１と電気的に分離された溝
２により、接合部分の空乏層電界を緩和でき、電界集中
による素子破壊を防止できる。Thus, according to this embodiment, a semiconductor substrate made of a material such as SiC, which is difficult to diffuse impurities, is used.
Even if there is no pn junction at the junction termination portion, the junction termination region 3
The groove 2 formed in the first electrode and electrically separated from the anode electrode 11 can alleviate the electric field of the depletion layer at the junction portion and prevent the element from being destroyed due to the electric field concentration.
【００２７】図３は、本発明の第２の実施例に係る高耐
圧半導体装置の構造を示す素子断面図である。なお、以
下、前出の図の高耐圧半導体装置と対応する部分には前
出の図と同一符号を付し、詳細な説明は省略する。FIG. 3 is an element sectional view showing the structure of a high breakdown voltage semiconductor device according to the second embodiment of the present invention. Note that, in the following, the portions corresponding to the high breakdown voltage semiconductor device in the above-mentioned figure are denoted by the same reference numerals as those in the above-mentioned figure, and detailed description will be omitted.
【００２８】本実施例の高耐圧半導体装置が先の実施例
のそれと異なる点は、接合終端領域３内の電位の浮いた
電極７を抵抗体１２を介してカソード電極９に接続し、
電極７の電位を固定したことにある。The high withstand voltage semiconductor device of this embodiment is different from that of the previous embodiment in that the electrode 7 having a floating potential in the junction termination region 3 is connected to the cathode electrode 9 via the resistor 12,
This is because the potential of the electrode 7 was fixed.
【００２９】このように構成された高耐圧半導体装置で
も先の実施例のそれと同様な効果が得られるのは勿論の
こと、本実施例では、電極７の電位がアノード電位とカ
ソード電位との間の電位に固定されているので、確実に
アノード電極６に遠い１対の溝２ほど大きい電位の電気
力線を集めることができ、空乏層電界を緩和できる電界
分布を確実に形成できる。The high withstand voltage semiconductor device constructed as described above can obtain the same effect as that of the previous embodiment, and in this embodiment, the potential of the electrode 7 is between the anode potential and the cathode potential. Since the electric field lines having a larger electric potential are more reliably collected in the pair of grooves 2 farther from the anode electrode 6, the electric field distribution capable of relaxing the depletion layer electric field can be surely formed.
【００３０】これは先の実施例のように電位に浮いた電
極７の電位が固定されていないと、電極７に電荷が溜ま
った場合に、溝２により形成された電界分布が変化し、
接合終端部の空乏層電界が強くなる恐れがあるからであ
る。This is because the electric field distribution formed by the groove 2 changes when electric charges are accumulated in the electrode 7 unless the electric potential of the electrode 7 floating at the electric potential is fixed as in the previous embodiment.
This is because the electric field of the depletion layer at the junction termination portion may become strong.
【００３１】なお、抵抗体１２の代わりにキャパシタ等
を用いても良い。A capacitor or the like may be used instead of the resistor 12.
【００３２】図４は、本発明の第３の実施例に係る高耐
圧半導体装置の平面図である。また、図５は、図４の一
点鎖線で囲まれた領域のより詳しい図であり、図５
（ａ）は平面図、図５（ｂ）は図５（ａ）のＢ−Ｂ´断
面図である。FIG. 4 is a plan view of a high breakdown voltage semiconductor device according to the third embodiment of the present invention. 5 is a more detailed view of the area surrounded by the one-dot chain line in FIG.
5A is a plan view, and FIG. 5B is a sectional view taken along line BB ′ of FIG.
【００３３】本実施例の高耐圧半導体装置がこれまでの
実施例のそれと異なる点は、主電流領域１の回りに連続
したリング状の溝の代わり、断続したリング状の溝２ａ
を設けたことにある。The high withstand voltage semiconductor device of this embodiment is different from that of the previous embodiments in that instead of the continuous ring-shaped groove around the main current region 1, the interrupted ring-shaped groove 2a is formed.
Has been established.
【００３４】このような構成にしても先の実施例と同様
な効果が得られる。なお、図３のように電位の浮いた電
極７ａを固定しても良い。また、リング状の代わりに
は、散乱的に溝２ａを設けても良い。Even with such a configuration, the same effect as that of the previous embodiment can be obtained. The electrode 7a having a floating electric potential may be fixed as shown in FIG. Further, instead of the ring shape, the grooves 2a may be provided in a scattered manner.
【００３５】図６は、本発明の第４の実施例に係る高耐
圧半導体装置の断面図である。FIG. 6 is a sectional view of a high breakdown voltage semiconductor device according to the fourth embodiment of the present invention.
【００３６】本実施例の高耐圧半導体装置が先の実施例
と異なる点は、１つの溝２ｂに１つの電位の浮いた電極
７ｂを設ける共に、電位の浮いた電極７ｂが溝２ｂから
横方向に引き出されていることにある。The high withstand voltage semiconductor device of this embodiment is different from the previous embodiments in that one groove 2b is provided with one electrode 7b with a floating potential, and the electrode 7b with a floating potential extends laterally from the groove 2b. Has been pulled out to.
【００３７】このように構成された高耐圧半導体装置で
は、電極７ｂがフイールドプレートの機能を果たすの
で、先の実施例に比べて、より高い空乏層電界の緩和が
期待できる。In the high breakdown voltage semiconductor device having such a structure, since the electrode 7b functions as a field plate, a higher relaxation of the depletion layer electric field can be expected as compared with the previous embodiment.
【００３８】図７は、本発明の第５の実施例に係る高耐
圧半導体装置の断面図である。FIG. 7 is a sectional view of a high breakdown voltage semiconductor device according to the fifth embodiment of the present invention.
【００３９】図中、３１は低濃度のｎ型ＳｉＣ基板を示
しており、その裏面側にはｐ型の半導体からなるコンタ
クト層３２を介してアノード電極３３が設けられてい
る。In the figure, reference numeral 31 denotes a low-concentration n-type SiC substrate, on the back side of which an anode electrode 33 is provided via a contact layer 32 made of a p-type semiconductor.
【００４０】ｎ型ＳｉＣ基板３１の表面下部にはＳｉＯ
2 膜等の絶縁膜３４が埋め込まれている。また、主電流
領域１のｎ型ＳｉＣ基板３１上には絶縁層３５に埋めこ
まれたゲート電極３６が設けられ、そして、カソード電
極３７がｎ型ＳｉＣ基板３１に接して設けられている。
このカソード電極３７とｎ型ＳｉＣ基板３１とでショッ
トキー接合が形成され、先の実施例と同様にショットキ
ーバリアダイオードが形成されいてる。SiO is formed below the surface of the n-type SiC substrate 31.
An insulating film 34 such as two films is embedded. A gate electrode 36 embedded in an insulating layer 35 is provided on the n-type SiC substrate 31 in the main current region 1, and a cathode electrode 37 is provided in contact with the n-type SiC substrate 31.
A Schottky junction is formed by the cathode electrode 37 and the n-type SiC substrate 31, and a Schottky barrier diode is formed as in the previous embodiment.
【００４１】一方、接合終端領域３のｎ型ＳｉＣ基板３
１上には絶縁膜３８が設けられ、この絶縁膜３８は電位
の浮いた電極３９で覆われている。この電位の浮いた電
極３９は絶縁層４０によって互いに電気的に分離されて
いる。On the other hand, the n-type SiC substrate 3 in the junction termination region 3
An insulating film 38 is provided on the first electrode 1, and the insulating film 38 is covered with an electrode 39 having a floating potential. The electrodes 39 having this floating potential are electrically separated from each other by the insulating layer 40.
【００４２】また、主電流領域１と接合終端領域３と境
界ではゲート電極３６ａ，絶縁層３５ａを共有している
場合もある。The gate electrode 36a and the insulating layer 35a may be shared at the boundary between the main current region 1 and the junction termination region 3.
【００４３】このように構成された高耐圧半導体装置に
高電圧の逆バイアス電圧が印加されると、接合終端領域
３内の基板表面の絶縁膜３８と基板中の２つの絶縁膜３
とからなる１組の絶縁膜が先の実施例の１対の溝と同様
な機能を果たす。When a high reverse bias voltage is applied to the high breakdown voltage semiconductor device thus configured, the insulating film 38 on the substrate surface in the junction termination region 3 and the two insulating films 3 in the substrate.
A pair of insulating films consisting of and fulfills the same function as the pair of grooves in the previous embodiment.
【００４４】この結果、接合終端部の空乏層電界を緩和
でき、電界集中による素子破壊を防止できる。なお、主
電流領域の絶縁膜３４は無くても良いが、あったほうが
空乏層電界を緩和する効果が高くなる。As a result, the electric field of the depletion layer at the junction termination portion can be relaxed and the element breakdown due to the electric field concentration can be prevented. Note that the insulating film 34 in the main current region may be omitted, but if it is present, the effect of alleviating the depletion layer electric field becomes higher.
【００４５】図８は、本発明の第６の実施例に係る高耐
圧半導体装置の断面図である。FIG. 8 is a sectional view of a high breakdown voltage semiconductor device according to the sixth embodiment of the present invention.
【００４６】本実施例の高耐圧半導体装置が先の実施例
と主として異なる点は、ｎ型ＳｉＣ基板３１内にｐ型半
導体層４２を設けたことにある。The high withstand voltage semiconductor device of this embodiment is mainly different from the previous embodiments in that the p-type semiconductor layer 42 is provided in the n-type SiC substrate 31.
【００４７】即ち、ｐ型半導体層４２と絶縁膜３４、ｐ
型半導体層４２と絶縁膜３８、ｐ型半導体層４２と電極
３９とが接触するようにｎ型ＳｉＣ基板３１内にｐ型半
導体層４２を設け、確実に絶縁膜３４と絶縁膜３８と電
極３９とが同電位になるようにしたことにある。これに
よって、絶縁膜３４と絶縁膜３８と電極３９による空乏
層電界の緩和の効果を向上することができる。That is, the p-type semiconductor layer 42 and the insulating film 34, p
The p-type semiconductor layer 42 is provided in the n-type SiC substrate 31 so that the p-type semiconductor layer 42 and the insulating film 38 are in contact with each other and the p-type semiconductor layer 42 and the electrode 39 are in contact with each other. This is because they have the same potential. Thereby, the effect of relaxing the depletion layer electric field by the insulating film 34, the insulating film 38, and the electrode 39 can be improved.
【００４８】また、図中、３４は紙面に垂直な方向にｐ
型半導体層とｎ型半導体層とが交互に並んだ半導体層を
示している。即ち、本実施例では、ショットキーバリア
ダイオードでなくＩＧＢＴが形成されている。In the figure, 34 is p in the direction perpendicular to the paper surface.
A semiconductor layer in which the type semiconductor layers and the n-type semiconductor layers are alternately arranged is shown. That is, in this embodiment, the IGBT is formed instead of the Schottky barrier diode.
【００４９】なお、本発明は上述した実施例に限定され
るものではない。例えば、上記実施例では、２つの溝ご
とに１つの電位が浮いた電極を設けた実施例があった
が、３つ，４つ或いはそれ以上の溝ごとに１つの電位が
浮いた電極を設けても良い。The present invention is not limited to the above embodiment. For example, in the above-described embodiment, there is an embodiment in which one electrode having a floating potential is provided for every two grooves, but one electrode having a floating potential is provided for each of three, four, or more grooves. May be.
【００５０】更に、２つの溝ごとに１つの電位が浮いた
電極と３つの溝ごとに１つの電位が浮いた電極とのよう
に、溝数の異なる電位の浮いた電極が混在しても良い。Furthermore, floating electrodes having different potentials may be mixed, such as an electrode in which one potential is floated for every two grooves and an electrode in which one potential is floated for every three grooves. .
【００５１】なお、上記実施例では溝内に金属材料を充
填したが、金属以外の導電材料、更には絶縁材料であっ
ても良い。Although the groove is filled with a metal material in the above embodiment, a conductive material other than metal or an insulating material may be used.
【００５２】更にまた、上記実施例を適宜組み合わせて
も良い。例えば、主電流領域のコーナー部では溝を断続
的（散乱的）に形成し、他の部分では連続な溝を形成す
る。これは特にコーナー部の曲率が大きい場合に有効で
ある。何故なら曲率が大きい部分があると連続したリン
グ状の溝の形成が困難になるからである。また、従来の
技術と組み合わせても良い。また、本発明は、ＳｉＣや
ダイヤモンドなど不純物拡散のしにくいものについて特
に効果があるが、Ｓｉ等でも良い。Furthermore, the above embodiments may be combined appropriately. For example, grooves are formed intermittently (scatteringly) at the corners of the main current region, and continuous grooves are formed at other portions. This is especially effective when the curvature of the corner is large. This is because it is difficult to form a continuous ring-shaped groove if there is a portion having a large curvature. Further, it may be combined with a conventional technique. Further, the present invention is particularly effective for those such as SiC and diamond which are less likely to diffuse impurities, but Si or the like may be used.
【００５３】その他、本発明の要旨を逸脱しない範囲
で、種々変形して実施できる。In addition, various modifications can be made without departing from the scope of the present invention.
【００５４】[0054]
【発明の効果】以上詳述したように本発明によれば、接
合終端部にｐｎ接合が無い場合や、ｐｎ接合の形成が困
難な拡散係数が小さい基板を用いた場合でも、耐圧が十
分大きい高耐圧半導体装置が得られる。As described in detail above, according to the present invention, the breakdown voltage is sufficiently high even when there is no pn junction at the junction termination portion or when a substrate having a small diffusion coefficient which makes it difficult to form a pn junction is used. A high breakdown voltage semiconductor device can be obtained.
【図１】本発明の第１の実施例に係る高耐圧半導体装置
の平面図。FIG. 1 is a plan view of a high breakdown voltage semiconductor device according to a first embodiment of the present invention.
【図２】図１の一点鎖線で囲まれた領域のより詳しい
図。FIG. 2 is a more detailed view of the area surrounded by the alternate long and short dash line in FIG.
【図３】本発明の第２の実施例に係る高耐圧半導体装置
の断面図。FIG. 3 is a sectional view of a high breakdown voltage semiconductor device according to a second embodiment of the present invention.
【図４】本発明の第３の実施例に係る高耐圧半導体装置
の平面図。FIG. 4 is a plan view of a high breakdown voltage semiconductor device according to a third embodiment of the present invention.
【図５】図４の一点鎖線で囲まれた領域のより詳しい
図。5 is a more detailed view of the area surrounded by the alternate long and short dash line in FIG.
【図６】本発明の第４の実施例に係る高耐圧半導体装置
の断面図。FIG. 6 is a sectional view of a high breakdown voltage semiconductor device according to a fourth embodiment of the present invention.
【図７】本発明の第５の実施例に係る高耐圧半導体装置
の断面図。FIG. 7 is a sectional view of a high breakdown voltage semiconductor device according to a fifth embodiment of the present invention.
【図８】本発明の第６の実施例に係る高耐圧半導体装置
の断面図。FIG. 8 is a sectional view of a high breakdown voltage semiconductor device according to a sixth embodiment of the present invention.
【図９】従来の高耐圧化の手法を説明するための図。FIG. 9 is a diagram for explaining a conventional method of increasing the withstand voltage.
１…主電流領域、２，２ａ…溝、３…接合終端領域、４
…溝、５…ＳｉＯ2 膜、６…アノード電極、７，７ａ…
電位の浮いた電極、８…コンタクト層、９…カソード電
極、１０…ｎ型ＳｉＣ基板、１２…抵抗体、３１…ｎ型
ＳｉＣ基板、３２…コンタクト層、３３…アノード電
極、３４…絶縁膜、３５…絶縁層、３６…ゲート電極、
３７…カソード電極、３８…絶縁膜、３９…電位の浮い
た電極、４０…絶縁層、４１…ｐ型半導体層。1 ... Main current region, 2, 2a ... Groove, 3 ... Junction termination region, 4
... Grooves, 5 ... SiO 2 film, 6 ... Anode electrode, 7, 7a ...
Electrodes with floating potential, 8 ... Contact layer, 9 ... Cathode electrode, 10 ... N-type SiC substrate, 12 ... Resistor, 31 ... N-type SiC substrate, 32 ... Contact layer, 33 ... Anode electrode, 34 ... Insulating film, 35 ... Insulating layer, 36 ... Gate electrode,
37 ... Cathode electrode, 38 ... Insulating film, 39 ... Electrode with floating potential, 40 ... Insulating layer, 41 ... P-type semiconductor layer.
Claims (1)
れる領域と、 前記主電流の流れる領域を囲むように形成され、且つ前
記主電流が流れる電極と電気的に分離された溝を内部に
有する接合終端領域とを具備してなることを特徴とする
高耐圧半導体装置。1. A region formed in a semiconductor substrate, in which a main current flows, and a groove formed so as to surround the region in which the main current flows and electrically isolated from an electrode in which the main current flows. A high breakdown voltage semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25658692A JP3297087B2 (en) | 1992-09-25 | 1992-09-25 | High voltage semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25658692A JP3297087B2 (en) | 1992-09-25 | 1992-09-25 | High voltage semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112216A true JPH06112216A (en) | 1994-04-22 |
| JP3297087B2 JP3297087B2 (en) | 2002-07-02 |
Family
ID=17294692
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25658692A Expired - Fee Related JP3297087B2 (en) | 1992-09-25 | 1992-09-25 | High voltage semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3297087B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0373848A2 (en) * | 1988-12-13 | 1990-06-20 | Sumitomo Chemical Company, Limited | Electrically conductive zirconia-based sintered body and process for the production thereof |
| JP2003068761A (en) * | 2001-08-29 | 2003-03-07 | Denso Corp | Silicon carbide semiconductor device and manufacture thereof |
| JP2006190882A (en) * | 2005-01-07 | 2006-07-20 | Shindengen Electric Mfg Co Ltd | Sic semiconductor device |
| JP2013055347A (en) * | 2012-11-08 | 2013-03-21 | Sanken Electric Co Ltd | Semiconductor device |
| US9099378B2 (en) | 2012-09-14 | 2015-08-04 | Hyundai Motor Company | Schottky barrier diode and method of manufacturing the same |
| WO2023112619A1 (en) * | 2021-12-19 | 2023-06-22 | 新電元工業株式会社 | Semiconductor device |
-
1992
- 1992-09-25 JP JP25658692A patent/JP3297087B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0373848A2 (en) * | 1988-12-13 | 1990-06-20 | Sumitomo Chemical Company, Limited | Electrically conductive zirconia-based sintered body and process for the production thereof |
| EP0373848A3 (en) * | 1988-12-13 | 1991-01-16 | Sumitomo Chemical Company, Limited | Electrically conductive zirconia-based sintered body and process for the production thereof |
| JP2003068761A (en) * | 2001-08-29 | 2003-03-07 | Denso Corp | Silicon carbide semiconductor device and manufacture thereof |
| JP2006190882A (en) * | 2005-01-07 | 2006-07-20 | Shindengen Electric Mfg Co Ltd | Sic semiconductor device |
| JP4527550B2 (en) * | 2005-01-07 | 2010-08-18 | 新電元工業株式会社 | SiC semiconductor device |
| US9099378B2 (en) | 2012-09-14 | 2015-08-04 | Hyundai Motor Company | Schottky barrier diode and method of manufacturing the same |
| JP2013055347A (en) * | 2012-11-08 | 2013-03-21 | Sanken Electric Co Ltd | Semiconductor device |
| WO2023112619A1 (en) * | 2021-12-19 | 2023-06-22 | 新電元工業株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3297087B2 (en) | 2002-07-02 |
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