JP4797274B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device and a method for manufacturing the same, and is particularly suitable for application to a J-FET.
[0002]
[Prior art]
FIG. 8 shows a cross-sectional configuration of an n-channel J-FET as an example of a SiC semiconductor device used as a power element. As shown in FIG. 8, the n-channel type J-FET is formed using a substrate obtained by growing an n ⁻ type epilayer J2 on an n ⁺ type substrate J1 made of SiC. A p-type first gate region J3 is formed in the surface layer portion of the n ⁻ -type epi layer J2. A channel layer J4 is formed on the n ⁻ -type epi layer J2 including the first base region J3. An n ⁺ -type source region J5 is formed in a region located above the first base region J3 in the channel layer J4. Further, a p-type second gate region J6 is formed on the surface of the channel layer J4 so as to overlap with a portion of the first gate region J3 that extends so as to protrude from the n ⁺ -type source region J5. ing. The first and second gate electrodes J7 and J8 are formed so as to be in contact with the first and second gate regions J3 and J6, and the source electrode J9 is formed so as to be in contact with the n ⁺ -type source region J5. Further, a drain electrode J10 is formed so as to be in contact with the n ⁺ type substrate J1, and the J-FET shown in FIG. 8 is configured.
[0003]
[Problems to be solved by the invention]
However, in such a normally-off J-FET, a parasitic diode is formed by the PN junction between the second gate region J6 and the channel region J4, and a leakage current flows through the parasitic diode, so that the J-FET There is a problem that the operation cannot be performed satisfactorily. In theory, this parasitic diode should not flow to the built-in potential (2.8 V) at the PN junction, but in reality, depending on the activation state of the impurities, the presence or absence of crystal defects, etc. Current flows at a lower voltage. According to experiments, when Al (aluminum) is used as the impurity of the second gate electrode J6 and the impurity concentration is 1 × 10 ¹⁹ cm ⁻³ , about 2.1 V is used, and B (boron) is used as the impurity and B In addition to the above, C (carbon) is implanted, the concentration of B is set to 1 × 10 ¹⁹ cm ⁻³ , and the concentration of C is set to 1 × 10 ²⁰ cm ⁻³ to reduce the diffusion amount of B. Current flowed through the parasitic diode at about .9V.
[0004]
In view of the above points, an object of the present invention is to prevent leakage current between a gate region and a channel region so that the silicon carbide semiconductor device can operate satisfactorily.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, in the invention described in claim 1, high resistance layers (4a, 6b) into which V is implanted are formed between the second gate region (6) and the channel layer (4). It is characterized by that. By adopting such a configuration, it becomes possible to prevent leakage current from flowing through the PN junction between the second gate region and the channel layer by the high resistance layer, so that the operation of the silicon carbide semiconductor device can be performed satisfactorily. It is possible to
[0006]
Specifically, the high resistance layer is positioned below the second gate region in the lower layer portion in the second gate region as shown in claim 2 or in the surface layer portion in the channel layer as shown in claim 3. It is formed in the site to do.
[0007]
The invention according to claims 5 to 11 relates to a method for manufacturing a silicon carbide semiconductor device according to claims 1 to 4. According to the inventions of the fifth to eleventh aspects, the silicon carbide semiconductor device having the above-described configuration can be manufactured. As shown in claim 7, the high resistance layer may be formed by ion implantation of V, and as shown in claim 8, the high resistance layer is formed by epitaxial growth under the condition where V is implanted. It may be formed.
[0008]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a cross-sectional structure of a double gate drive type n-channel J-FET as a silicon carbide semiconductor device according to the first embodiment of the present invention. Hereinafter, the configuration of the J-FET will be described with reference to FIG.
[0010]
FIG. 1 shows a cross-sectional configuration of one cell of a J-FET. The n ⁺ type substrate 1 made of silicon carbide has an upper surface as a main surface and a lower surface opposite to the main surface as a back surface. On the main surface of n ⁺ type substrate 1, n ⁻ type epi layer 2 made of silicon carbide having a dopant concentration lower than that of substrate 1 is epitaxially grown.
[0011]
In a predetermined region in the surface layer portion of the n ⁻ type epi layer 2, a first gate region 3 made of a p ⁺ type layer is formed substantially symmetrically on the left and right sides of the paper. A channel layer 4 composed of an n ⁻ -type layer is epitaxially grown on the surface of the n ⁻ -type epi layer 2 including the first gate region 3. An n ⁺ type source region 5 is formed in a portion of the surface layer portion of the channel layer 4 located above the first gate region 3. In addition, a second gate region 6 is formed in a portion located on at least the first gate region 3 on the surface of the channel layer 4. In the second gate region 6, the side away from the channel layer 4 is constituted by the p ⁺ -type layer 6 a and the side in contact with the channel layer 4 is constituted by the high resistance layer 6 b.
[0012]
A contact region 7 reaching the first gate region 3 is formed in the channel layer 4, and a first gate electrode 8 electrically connected to the first gate region 3 is formed on the contact region 7. Has been. Further, on the n ⁺ -type source region 5, the source electrode 9 electrically connected to the n ⁺ -type source region 5 is formed, on the second gate region 6, p in the second gate region 6 ^A second gate electrode 10 electrically connected to the ⁺ type layer 6a is formed. Then, on the back side of the n ⁺ -type substrate 1, n ⁺ -type substrate 1 and electrically connected to the drain electrode 11 are formed, J-FET is formed in this embodiment.
[0013]
The J-FET configured as described above is configured to operate in a normally-off type. That is, when no voltage is applied to the first and second gate electrodes 8 and 10, the channel layer 4 is pinched off by the depletion layer extending from the first and second gate regions 3 and 6. When a desired voltage is applied to the first and second gate electrodes 8, 10, the depletion layer extends from the first to second gate regions 3, 6, a channel is formed, and the source electrode 9 is formed. The current flows in the order of n ⁺ type source region 5 → channel layer 4 → n ⁻ type epi layer 2 → n ⁺ type substrate 1 → drain electrode 11.
[0014]
Such a J-FET has a configuration in which a high resistance layer 6b is provided between a p ⁺ type layer 6a provided in the second gate region 6 and a channel layer 4 made of an n ⁻ type layer. The high resistance layer 6b is configured by ion-implanting V (vanadium) into the lower layer portion of the second gate region 6 configured by p ⁺ type, thereby making the region substantially i-type. For example, in p-type 6H-SiC in which V is ion-implanted, a deep level is formed at 1.4 eV, and when V is implanted into the p-type region, the deep level compensates for acceptor level holes, resulting in high resistance. Layer 6b is formed.
[0015]
As described above, since the high resistance layer 6b is provided, it is possible to prevent the leakage current from flowing to the PN junction between the p ⁺ type layer 6a and the channel layer 4 by the high resistance layer 6b. As a result, leakage current due to the parasitic diode can be prevented, and the J-FET can be operated satisfactorily. Further, since the high resistance layer 6b formed by implanting V becomes close to a non-doped state, it is possible to prevent the depletion layer from the second gate region 6 from being greatly affected. For this reason, the off-characteristics of the J-FET are not adversely affected.
[0016]
Next, the manufacturing process of the J-FET shown in FIG. 1 will be described with reference to FIGS.
[0017]
[Step shown in FIG. 2 (a)]
First, an n-type 4H, 6H, 3C or 15R-SiC substrate, that is, an n ⁺ -type substrate 1 is prepared. For example, an n ⁺ type substrate 1 having a thickness of 400 μm and a main surface of (0001) Si plane or (112-0) a plane is prepared. Then, an n ⁻ type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface of the substrate 1. In this case, the n ⁻ -type epi layer 2 has the same crystal as the underlying substrate 1 and becomes an n-type 4H, 6H, 3C, or 15R—SiC layer.
[0018]
After an LTO (Low Temperature Oxide) film 20 is disposed in a predetermined region on the n ⁻ -type epi layer 2, the LTO film 20 is patterned by photolithography to open the predetermined region. Then, ion implantation is performed using the LTO film 20 as a mask. Specifically, B or Al is ion-implanted as a p-type impurity at a position where the first gate region 3 is to be formed.
[0019]
[Step shown in FIG. 2 (b)]
After the LTO film 20 is removed, the implanted ions are activated by performing an annealing process using a heating furnace or RTA (short time annealing) to form the first gate region 3. In the formation of the first gate region 3, if it is not desired to thermally diffuse the p-type impurity, Al which is difficult to thermally diffuse is used, or a certain ratio of carbon to boron (preferably boron: carbon = 1: 10) It is preferable that the thermal diffusion is difficult by injection.
[0020]
[Step shown in FIG. 3 (a)]
A channel layer 4 made of an n ⁻ -type layer is formed by epitaxial growth on the n ⁻ -type epi layer 2 including the first gate region 3. At this time, the impurity concentration of the channel layer 4 is preferably lower than that of the n ⁻ -type epi layer 2 in order to make it easier to obtain a normally-off type J-FET.
[0021]
[Step shown in FIG. 3B]
The second gate region 6 made of a p ⁺ type layer is formed by epitaxial growth so that the surface of the channel layer 4 is doped with a high concentration of p type impurities.
[0022]
[Step shown in FIG. 4 (a)]
V ions are implanted from the surface of the second gate region 6. At this time, V is implanted into the lower layer portion of the second gate region 6. As a result, the acceptor level holes are compensated by the deep level, so that the region into which V is injected is substantially i-type, and the high resistance layer 6b is formed.
[0023]
[Step shown in FIG. 4B]
After the LTO film 21 serving as a mask material is formed, the LTO film 21 is patterned by photolithography, leaving the LTO film 21 only in the portion corresponding to the second gate region 6.
[0024]
[Step shown in FIG. 5A]
The second gate region 6 is patterned by performing etching using the LTO film 21 as a mask.
[0025]
[Step shown in FIG. 5B]
After removing the LTO film 21, an LTO film 22 serving as a mask material is formed, and the LTO film 22 is patterned by photolithography, and the LTO film 22 is opened at a position where the contact region 7 is to be formed. Then, the contact region 7 is formed by ion implantation of B or Al, which is a p-type impurity, using the LTO film 22 as a mask.
[0026]
[Step shown in FIG. 6A]
After removing the LTO film 22, an LTO film 23 serving as a mask material is formed, and the LTO film 23 is patterned by photolithography, thereby opening the LTO film 23 at a position where the n ⁺ -type source region 5 is to be formed. Then, n ⁺ type source region 5 is formed by ion implantation of N (nitrogen) or P (phosphorus), or N and P, which are n type impurities, using LTO film 23 as a mask.
[0027]
[Step shown in FIG. 6B]
After removing the LTO film 23, n-type impurities and p-type impurities are activated by an annealing process using a heating furnace or RTA. Although the subsequent steps are not shown, first, after forming an interlayer insulating film on the surface side of the substrate, the interlayer insulating film is patterned to form the first and second gate regions 3 and 6 and the n ⁺ type source region 5. A communicating contact hole is formed. Thereafter, after forming an electrode layer on the interlayer insulating film, the source electrode 9 and the first and second gate electrodes 8 and 10 are formed by patterning the electrode layer, and the drain electrode 11 is further formed on the back side of the substrate. By forming, the J-FET shown in FIG. 1 is completed.
[0028]
As described above, by ion-implanting V into the lower layer portion of the second gate region 6 constituted by the p ⁺ -type layer, the region can be made the high resistance layer 6b, and the high resistance layer 6b makes the parasitic It is possible to prevent leakage current from flowing through the diode.
[0029]
(Second Embodiment)
FIG. 7 shows a cross-sectional configuration of the J-FET in the second embodiment of the present invention. As shown in FIG. 7, in the J-FET of the present embodiment, instead of the high resistance layer 6 b (see FIG. 1) formed in the lower layer portion of the second gate region 6, The difference from the first embodiment is that a high resistance layer 4a is provided in a portion located below the second gate region 6. Others are the same as in the first embodiment.
[0030]
As described above, even when the high resistance layer 4a is formed on the surface layer portion of the channel layer 4, a leakage current is caused in the parasitic diode by the second gate region 6 made of the p ⁺ type layer and the channel layer 4 made of the n ⁻ type layer. Can be prevented from flowing.
[0031]
In addition, the manufacturing method of the J-FET in this embodiment is almost the same as that of the first embodiment, but the process of FIG. 3A is performed instead of the process shown in FIG. 4A of the first embodiment. The J-FET in this embodiment can be manufactured by performing a V ion implantation step later. However, an ion implantation mask is provided on the channel layer 4 so that V is implanted only in a portion located below the second gate region 6 in the surface layer portion of the channel layer 4 during the ion implantation of V at this time. Need to be placed.
[0032]
Thus, in n-type 6H-SiC in which V is ion-implanted, the deep level is formed at 0.7 eV, and when V is injected into the n-type region, the deep level compensates for electrons at the donor level. A high resistance layer 4a is formed. Even when such a high resistance layer 4a is used, the same effect as that of the first embodiment can be obtained.
[0033]
(Other embodiments)
In each of the above embodiments, the J-FET having a double gate structure capable of controlling both the potentials in the first and second gate regions 3 and 6 has been described. However, only one of the first and second gate regions 3 and 6 is described. The embodiments described above can also be applied to a J-FET having a single gate structure in which the potential of the above can be controlled. In that case, one of the first and second gate electrodes 8 and 10 is connected to the source electrode 9.
[0034]
In the present embodiment, the case where the high resistance layer 6a and the like are formed by ion implantation has been described. For example, by changing the epitaxial growth conditions in the first embodiment, the high resistance layer into which V is implanted during the epitaxial growth. 6a may be formed.
[0035]
In the above embodiment, the n-channel type J-FET has been described, but the present invention can of course be applied to a J-FET in which the conductivity type of each component is reversed.
[Brief description of the drawings]
FIG. 1 is a diagram showing a manufacturing process of a J-FET in a first embodiment of the present invention.
2 is a diagram showing a manufacturing process of the J-FET shown in FIG. 1. FIG.
FIG. 3 is a diagram illustrating a manufacturing process of the J-FET following FIG. 2;
4 is a diagram showing manufacturing steps of the J-FET following FIG. 3. FIG.
FIG. 5 is a diagram showing a manufacturing process of the J-FET following FIG. 4;
6 is a diagram showing a manufacturing process of the J-FET following FIG. 5. FIG.
FIG. 7 is a diagram showing a cross-sectional configuration of a J-FET in a second embodiment of the present invention.
FIG. 8 is a diagram showing a cross-sectional configuration of a conventional J-FET.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... n ^<+> type | mold substrate, 2 ... n < ^- > type | mold epilayer, 3 ... 1st gate region, 4 ... channel layer,
4a ... high resistance layer, 5 ... n ⁺ type source region, 6 ... second gate region,
6a ... p ⁺ type region, 6b ... high resistance layer, 7 ... contact region,
8, 10 ... 1st, 2nd gate electrode, 9 ... Source electrode, 11 ... Drain electrode.

Claims (11)

A first conductivity type semiconductor substrate (1) made of silicon carbide;
A first conductivity type semiconductor layer (2) made of silicon carbide formed on a main surface of the semiconductor substrate and having a higher resistance than the semiconductor substrate;
A first conductivity type first gate region (3) formed in a predetermined region of a surface layer portion of the semiconductor layer and having a predetermined depth;
A first conductivity type channel layer (4) formed on the semiconductor layer and the first gate region;
A source region (5) of a first conductivity type formed in a portion of the channel layer located above the first gate region;
A second gate region (6) of the second conductivity type formed so as to include a portion facing the first gate region on the channel layer or in a surface layer portion of the channel layer;
A source electrode (9) electrically connected to the source region;
A first gate electrode (8) electrically connected to the first gate region;
A second gate electrode (10) electrically connected to the second gate region;
A drain electrode (11) formed on the back side of the semiconductor substrate;
A silicon carbide semiconductor device, wherein high resistance layers (4a, 6b) into which V is implanted are formed between the second gate region and the channel layer. The silicon carbide semiconductor device according to claim 1, wherein the high resistance layer is formed in a lower layer portion of the second gate region. 3. The silicon carbide semiconductor device according to claim 1, wherein the high resistance layer is formed in a portion of the surface layer portion of the channel layer that is positioned below the second gate region. 4. It is a normally-off type in which the channel layer is pinched off by a depletion layer extending from the first and second gate regions in a state where no voltage is applied to the first and second gate electrodes. The silicon carbide semiconductor device according to any one of claims 1 to 3. Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of the first conductive type semiconductor substrate (1) made of silicon carbide;
Forming a second conductivity type first gate region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a channel layer (4) of a first conductivity type on the semiconductor layer and the first gate region;
Forming a second conductivity type second gate region (6) on the channel layer or in a surface layer portion of the channel layer so as to include a portion facing the first gate region;
Forming a first conductivity type source region (5) in a portion of the channel layer located on the first gate region;
A source electrode (9) electrically connected to the source region, a first gate electrode (8) electrically connected to the first gate region, and a second electrically connected to the second gate region. Forming a gate electrode (10);
Forming a drain electrode (11) on the back side of the semiconductor substrate, and a method for manufacturing a silicon carbide semiconductor device,
In the step of forming the second gate region, a method of forming a high resistance layer (6b) in which V is implanted in a lower layer portion of the second gate region is performed. Forming a first conductive type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate on a main surface of the first conductive type semiconductor substrate (1) made of silicon carbide;
Forming a second conductivity type first gate region (3) having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer;
Forming a channel layer (4) of a first conductivity type on the semiconductor layer and the first gate region;
Forming a second conductivity type second gate region (6) on the channel layer or in a surface layer portion of the channel layer so as to include a portion facing the first gate region;
Forming a first conductivity type source region (5) in a portion of the channel layer located on the first gate region;
A source electrode (9) electrically connected to the source region, a first gate electrode (8) electrically connected to the first gate region, and a second electrically connected to the second gate region. Forming a gate electrode (10);
Forming a drain electrode (11) on the back side of the semiconductor substrate, and a method for manufacturing a silicon carbide semiconductor device,
The step of forming the channel layer includes a step of forming a high resistance layer (6b) in which V is implanted in a portion of the surface layer portion of the channel layer located below the second gate region. A method for manufacturing a silicon carbide semiconductor device. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the step of forming the high resistance layer, the high resistance layer is formed by ion implantation of V. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the step of forming the high resistance layer, the high resistance layer is formed by epitaxial growth under a condition in which V is implanted. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein an impurity concentration of the channel layer is lower than that of the semiconductor layer. 10. The step of forming the first and / or second gate region uses Al or B and C as a second conductivity type impurity for the first and / or second gate. The manufacturing method of the silicon carbide semiconductor device as described in any one of these. 11. The method according to claim 5, wherein in the step of forming the source region, N, P, or N and P is used as a first conductivity type impurity for forming the source region. A method for manufacturing a silicon carbide semiconductor device.

Images