JP2002110827A5 - - Google Patents

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Publication number
JP2002110827A5
JP2002110827A5 JP2000301380A JP2000301380A JP2002110827A5 JP 2002110827 A5 JP2002110827 A5 JP 2002110827A5 JP 2000301380 A JP2000301380 A JP 2000301380A JP 2000301380 A JP2000301380 A JP 2000301380A JP 2002110827 A5 JP2002110827 A5 JP 2002110827A5
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JP
Japan
Prior art keywords
conductive layer
region
semiconductor substrate
element isolation
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000301380A
Other languages
English (en)
Japanese (ja)
Other versions
JP4064611B2 (ja
JP2002110827A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2000301380A priority Critical patent/JP4064611B2/ja
Priority claimed from JP2000301380A external-priority patent/JP4064611B2/ja
Priority to US09/916,595 priority patent/US6590255B2/en
Publication of JP2002110827A publication Critical patent/JP2002110827A/ja
Priority to US10/455,427 priority patent/US6995425B2/en
Publication of JP2002110827A5 publication Critical patent/JP2002110827A5/ja
Priority to US11/283,742 priority patent/US7442985B2/en
Application granted granted Critical
Publication of JP4064611B2 publication Critical patent/JP4064611B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000301380A 2000-09-29 2000-09-29 半導体装置 Expired - Fee Related JP4064611B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000301380A JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置
US09/916,595 US6590255B2 (en) 2000-09-29 2001-07-30 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US10/455,427 US6995425B2 (en) 2000-09-29 2003-06-06 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US11/283,742 US7442985B2 (en) 2000-09-29 2005-11-22 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000301380A JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置

Publications (3)

Publication Number Publication Date
JP2002110827A JP2002110827A (ja) 2002-04-12
JP2002110827A5 true JP2002110827A5 (https=) 2005-06-09
JP4064611B2 JP4064611B2 (ja) 2008-03-19

Family

ID=18782925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000301380A Expired - Fee Related JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置

Country Status (1)

Country Link
JP (1) JP4064611B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100520681B1 (ko) * 2002-12-23 2005-10-11 주식회사 하이닉스반도체 플래시 메모리 소자의 플로팅 게이트 형성방법
KR100557548B1 (ko) * 2003-03-11 2006-03-03 주식회사 하이닉스반도체 반도체소자의 형성방법
KR100541554B1 (ko) * 2003-12-09 2006-01-12 삼성전자주식회사 플래쉬 메모리 소자의 제조방법 및 그에 의해 제조된플래쉬 메모리 소자
JP4761745B2 (ja) * 2004-09-21 2011-08-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4129009B2 (ja) 2005-05-31 2008-07-30 株式会社東芝 半導体集積回路装置
KR100632645B1 (ko) * 2005-08-03 2006-10-11 주식회사 하이닉스반도체 바저항 측정패턴을 갖는 플래쉬 메모리 소자 및 그의형성방법
KR100672160B1 (ko) * 2005-12-28 2007-01-19 주식회사 하이닉스반도체 플래쉬 메모리 소자의 레지스터 형성방법
JP2008103682A (ja) * 2006-09-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010177694A (ja) * 2010-04-07 2010-08-12 Renesas Electronics Corp 半導体装置

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