JP4064611B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP4064611B2
JP4064611B2 JP2000301380A JP2000301380A JP4064611B2 JP 4064611 B2 JP4064611 B2 JP 4064611B2 JP 2000301380 A JP2000301380 A JP 2000301380A JP 2000301380 A JP2000301380 A JP 2000301380A JP 4064611 B2 JP4064611 B2 JP 4064611B2
Authority
JP
Japan
Prior art keywords
conductive layer
region
element isolation
semiconductor substrate
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000301380A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002110827A5 (https=
JP2002110827A (ja
Inventor
正之 市毛
祐司 竹内
理一郎 白田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000301380A priority Critical patent/JP4064611B2/ja
Priority to US09/916,595 priority patent/US6590255B2/en
Publication of JP2002110827A publication Critical patent/JP2002110827A/ja
Priority to US10/455,427 priority patent/US6995425B2/en
Publication of JP2002110827A5 publication Critical patent/JP2002110827A5/ja
Priority to US11/283,742 priority patent/US7442985B2/en
Application granted granted Critical
Publication of JP4064611B2 publication Critical patent/JP4064611B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2000301380A 2000-09-29 2000-09-29 半導体装置 Expired - Fee Related JP4064611B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000301380A JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置
US09/916,595 US6590255B2 (en) 2000-09-29 2001-07-30 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US10/455,427 US6995425B2 (en) 2000-09-29 2003-06-06 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US11/283,742 US7442985B2 (en) 2000-09-29 2005-11-22 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000301380A JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置

Publications (3)

Publication Number Publication Date
JP2002110827A JP2002110827A (ja) 2002-04-12
JP2002110827A5 JP2002110827A5 (https=) 2005-06-09
JP4064611B2 true JP4064611B2 (ja) 2008-03-19

Family

ID=18782925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000301380A Expired - Fee Related JP4064611B2 (ja) 2000-09-29 2000-09-29 半導体装置

Country Status (1)

Country Link
JP (1) JP4064611B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100520681B1 (ko) * 2002-12-23 2005-10-11 주식회사 하이닉스반도체 플래시 메모리 소자의 플로팅 게이트 형성방법
KR100557548B1 (ko) * 2003-03-11 2006-03-03 주식회사 하이닉스반도체 반도체소자의 형성방법
KR100541554B1 (ko) * 2003-12-09 2006-01-12 삼성전자주식회사 플래쉬 메모리 소자의 제조방법 및 그에 의해 제조된플래쉬 메모리 소자
JP4761745B2 (ja) * 2004-09-21 2011-08-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4129009B2 (ja) 2005-05-31 2008-07-30 株式会社東芝 半導体集積回路装置
KR100632645B1 (ko) * 2005-08-03 2006-10-11 주식회사 하이닉스반도체 바저항 측정패턴을 갖는 플래쉬 메모리 소자 및 그의형성방법
KR100672160B1 (ko) * 2005-12-28 2007-01-19 주식회사 하이닉스반도체 플래쉬 메모리 소자의 레지스터 형성방법
JP2008103682A (ja) * 2006-09-20 2008-05-01 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010177694A (ja) * 2010-04-07 2010-08-12 Renesas Electronics Corp 半導体装置

Also Published As

Publication number Publication date
JP2002110827A (ja) 2002-04-12

Similar Documents

Publication Publication Date Title
JP4160283B2 (ja) 半導体装置の製造方法
US6222225B1 (en) Semiconductor device and manufacturing method thereof
JP3512976B2 (ja) 不揮発性半導体記憶装置およびその製造方法
US6153472A (en) Method for fabricating a flash memory
US6573545B2 (en) Semiconductor memory device for eliminating floating body effect and method of fabricating the same
US8163608B2 (en) Methods of fabricating nonvolatile memory devices
JP4068286B2 (ja) 半導体装置の製造方法
WO2001067517A1 (en) Semiconductor device and method of manufacturing the same.
JPH11163304A (ja) 不揮発性半導体記憶装置及びその製造方法
CN100550353C (zh) 半导体器件及其制造方法
US20090026525A1 (en) Memory and method for fabricating the same
US6995425B2 (en) Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
JP4080485B2 (ja) ビット線構造およびその製造方法
US20080087981A1 (en) Semiconductor device and method of fabricating the same
JP4064611B2 (ja) 半導体装置
KR100660543B1 (ko) 낸드형 플래시 메모리 장치 및 그 제조 방법
US20060017111A1 (en) Semiconductor device and method of fabricating the same
US7541243B2 (en) Methods of forming integrated circuit devices having gate electrodes formed on non-uniformly thick gate insulating layers
US20040183139A1 (en) Self-aligned trench isolation method and semiconductor device fabricated using the same
KR100538075B1 (ko) 플래시 메모리 소자의 제조 방법
JP2001156269A (ja) 半導体記憶装置及びその製造方法
JP4955880B2 (ja) 基板内にトレンチを形成する集積回路を製作するための方法
US7511330B2 (en) Semiconductor device and method of fabricating the same
JP2004356428A (ja) 不揮発性半導体記憶装置、及び、その製造方法
KR20040029525A (ko) 플레쉬 메모리 소자 및 그 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040826

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040826

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060327

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071002

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071203

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071225

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071227

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110111

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120111

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130111

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees