JP2001268893A5 - - Google Patents

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Publication number
JP2001268893A5
JP2001268893A5 JP2000080410A JP2000080410A JP2001268893A5 JP 2001268893 A5 JP2001268893 A5 JP 2001268893A5 JP 2000080410 A JP2000080410 A JP 2000080410A JP 2000080410 A JP2000080410 A JP 2000080410A JP 2001268893 A5 JP2001268893 A5 JP 2001268893A5
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JP
Japan
Prior art keywords
potential
output
voltage
electrode
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000080410A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001268893A (ja
JP3872927B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2000080410A priority Critical patent/JP3872927B2/ja
Priority claimed from JP2000080410A external-priority patent/JP3872927B2/ja
Priority to US09/812,573 priority patent/US6456541B2/en
Publication of JP2001268893A publication Critical patent/JP2001268893A/ja
Priority to US10/212,062 priority patent/US6614699B2/en
Publication of JP2001268893A5 publication Critical patent/JP2001268893A5/ja
Application granted granted Critical
Publication of JP3872927B2 publication Critical patent/JP3872927B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000080410A 2000-03-22 2000-03-22 昇圧回路 Expired - Fee Related JP3872927B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000080410A JP3872927B2 (ja) 2000-03-22 2000-03-22 昇圧回路
US09/812,573 US6456541B2 (en) 2000-03-22 2001-03-21 Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases
US10/212,062 US6614699B2 (en) 2000-03-22 2002-08-06 Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000080410A JP3872927B2 (ja) 2000-03-22 2000-03-22 昇圧回路

Publications (3)

Publication Number Publication Date
JP2001268893A JP2001268893A (ja) 2001-09-28
JP2001268893A5 true JP2001268893A5 (enExample) 2005-07-21
JP3872927B2 JP3872927B2 (ja) 2007-01-24

Family

ID=18597515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000080410A Expired - Fee Related JP3872927B2 (ja) 2000-03-22 2000-03-22 昇圧回路

Country Status (2)

Country Link
US (2) US6456541B2 (enExample)
JP (1) JP3872927B2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3872927B2 (ja) * 2000-03-22 2007-01-24 株式会社東芝 昇圧回路
JP4149637B2 (ja) * 2000-05-25 2008-09-10 株式会社東芝 半導体装置
JP2002009780A (ja) * 2000-06-16 2002-01-11 Mitsubishi Electric Corp 動的帯域割当システム及び動的帯域割当方法
US7053945B1 (en) * 2000-07-26 2006-05-30 Micron Technolopgy, Inc. Image sensor having boosted reset
CN1219352C (zh) 2001-12-17 2005-09-14 松下电器产业株式会社 放大电路
US6919236B2 (en) * 2002-03-21 2005-07-19 Advanced Micro Devices, Inc. Biased, triple-well fully depleted SOI structure, and various methods of making and operating same
US6878981B2 (en) * 2003-03-20 2005-04-12 Tower Semiconductor Ltd. Triple-well charge pump stage with no threshold voltage back-bias effect
CN100423421C (zh) * 2003-05-13 2008-10-01 富士通株式会社 半导体集成电路装置
US20050077950A1 (en) * 2003-10-14 2005-04-14 Robinson Curtis B. Negative charge pump
US7149132B2 (en) * 2004-09-24 2006-12-12 Ovonyx, Inc. Biasing circuit for use in a non-volatile memory device
US7323926B2 (en) * 2004-12-21 2008-01-29 Macronix International Co., Ltd. Charge pump circuit
KR100732756B1 (ko) * 2005-04-08 2007-06-27 주식회사 하이닉스반도체 전압 펌핑장치
KR100773348B1 (ko) * 2005-06-24 2007-11-05 삼성전자주식회사 고전압 발생회로 및 이를 구비한 반도체 메모리 장치
JP4170339B2 (ja) * 2005-12-22 2008-10-22 松下電器産業株式会社 昇圧回路
KR100780768B1 (ko) * 2006-04-12 2007-11-30 주식회사 하이닉스반도체 고전압 펌핑장치
US7512015B1 (en) * 2006-07-17 2009-03-31 Lattice Semiconductor Corporation Negative voltage blocking for embedded memories
JP4805748B2 (ja) * 2006-07-28 2011-11-02 Ｏｋｉセミコンダクタ株式会社 昇圧回路
US7619945B2 (en) * 2006-08-18 2009-11-17 Unity Semiconductor Corporation Memory power management
US8232833B2 (en) 2007-05-23 2012-07-31 Silicon Storage Technology, Inc. Charge pump systems and methods
US7592857B2 (en) * 2007-12-21 2009-09-22 G-Time Electronic Co., Ltd. Charge pump circuit
JP5361346B2 (ja) * 2008-11-21 2013-12-04 株式会社東芝 半導体集積回路
JP5317335B2 (ja) * 2009-01-29 2013-10-16 セイコーインスツル株式会社 昇圧回路
JP5315087B2 (ja) * 2009-02-20 2013-10-16 セイコーインスツル株式会社 昇圧回路
US9111601B2 (en) 2012-06-08 2015-08-18 Qualcomm Incorporated Negative voltage generators
US9391597B2 (en) 2013-11-12 2016-07-12 Macronix International Co., Ltd. Boost circuit
TWI559685B (zh) * 2013-11-21 2016-11-21 旺宏電子股份有限公司 升壓電路及控制升壓信號之輸出之方法
CN104682701B (zh) * 2013-11-26 2017-04-26 旺宏电子股份有限公司 升压电路
US11437097B2 (en) * 2020-12-09 2022-09-06 Micron Technology, Inc. Voltage equalization for pillars of a memory array

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07123163B2 (ja) * 1989-07-21 1995-12-25 日本電気株式会社 電荷転送装置
TW231343B (enExample) * 1992-03-17 1994-10-01 Hitachi Seisakusyo Kk
JPH07130175A (ja) * 1993-09-10 1995-05-19 Toshiba Corp 半導体記憶装置
US5856918A (en) * 1995-11-08 1999-01-05 Sony Corporation Internal power supply circuit
JP3497708B2 (ja) * 1997-10-09 2004-02-16 株式会社東芝 半導体集積回路
JP2000347755A (ja) * 1999-06-09 2000-12-15 Mitsubishi Electric Corp 半導体装置
JP2001238435A (ja) * 2000-02-25 2001-08-31 Nec Corp 電圧変換回路
JP3872927B2 (ja) * 2000-03-22 2007-01-24 株式会社東芝 昇圧回路
JP5041631B2 (ja) * 2001-06-15 2012-10-03 ルネサスエレクトロニクス株式会社 半導体記憶装置

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