JP2001184300A - データ処理プロセッサ - Google Patents

データ処理プロセッサ

Info

Publication number
JP2001184300A
JP2001184300A JP36880099A JP36880099A JP2001184300A JP 2001184300 A JP2001184300 A JP 2001184300A JP 36880099 A JP36880099 A JP 36880099A JP 36880099 A JP36880099 A JP 36880099A JP 2001184300 A JP2001184300 A JP 2001184300A
Authority
JP
Japan
Prior art keywords
bus
value
channel
timer
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36880099A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001184300A5 (enExample
Inventor
Hiroshi Yamada
博 山田
Jinichi Hori
仁一 堀
Akira Hase
昌 長谷
Tetsuya Yamato
哲也 大和
Norihiko Sugita
憲彦 杉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP36880099A priority Critical patent/JP2001184300A/ja
Priority to US09/745,928 priority patent/US6658511B2/en
Publication of JP2001184300A publication Critical patent/JP2001184300A/ja
Priority to US10/673,851 priority patent/US6944696B2/en
Publication of JP2001184300A5 publication Critical patent/JP2001184300A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
JP36880099A 1999-12-27 1999-12-27 データ処理プロセッサ Pending JP2001184300A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP36880099A JP2001184300A (ja) 1999-12-27 1999-12-27 データ処理プロセッサ
US09/745,928 US6658511B2 (en) 1999-12-27 2000-12-26 Data processing processor
US10/673,851 US6944696B2 (en) 1999-12-27 2003-09-30 Data processing processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36880099A JP2001184300A (ja) 1999-12-27 1999-12-27 データ処理プロセッサ

Publications (2)

Publication Number Publication Date
JP2001184300A true JP2001184300A (ja) 2001-07-06
JP2001184300A5 JP2001184300A5 (enExample) 2004-09-24

Family

ID=18492793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36880099A Pending JP2001184300A (ja) 1999-12-27 1999-12-27 データ処理プロセッサ

Country Status (2)

Country Link
US (2) US6658511B2 (enExample)
JP (1) JP2001184300A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231477B2 (en) 2003-03-19 2007-06-12 Matsushita Electric Industrial Co., Ltd. Bus controller
JP2007164428A (ja) * 2005-12-13 2007-06-28 Oki Electric Ind Co Ltd バス調停回路及びそれを用いたマルチレイヤバスシステム

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001184300A (ja) * 1999-12-27 2001-07-06 Hitachi Ltd データ処理プロセッサ
JP2003058272A (ja) * 2001-08-21 2003-02-28 Mitsubishi Electric Corp 半導体装置およびそれに用いられる半導体チップ
JP4624715B2 (ja) * 2004-05-13 2011-02-02 ルネサスエレクトロニクス株式会社 システムｌｓｉ
CN100365602C (zh) * 2004-12-31 2008-01-30 北京中星微电子有限公司 实现多个主动装置对单一总线上从动装置进行存取的设备
FR2888017B1 (fr) * 2005-07-01 2007-08-31 Atmel Nantes Sa Sa Dispositif d'arbitrage asynchrone et microcontroleur comprenant un tel dispositif d'arbitrage
JP2008130056A (ja) * 2006-11-27 2008-06-05 Renesas Technology Corp 半導体回路
GB2447690B (en) * 2007-03-22 2011-06-08 Advanced Risc Mach Ltd A Data processing apparatus and method for performing multi-cycle arbitration
TWI463322B (zh) * 2009-08-06 2014-12-01 Asustek Comp Inc 具有雙主機之電腦系統
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
KR20170089678A (ko) * 2016-01-27 2017-08-04 한국전자통신연구원 처리 유닛, 인-메모리 데이터 처리 장치 및 방법

Family Cites Families (16)

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US5016162A (en) * 1988-03-30 1991-05-14 Data General Corp. Contention revolution in a digital computer system
US5105424A (en) * 1988-06-02 1992-04-14 California Institute Of Technology Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network
JP2659557B2 (ja) * 1988-07-27 1997-09-30 株式会社日立製作所 描画システム及び描画方法
JPH03263158A (ja) 1990-03-13 1991-11-22 Nec Corp 共通バス調停制御方式
JP3263158B2 (ja) 1992-12-21 2002-03-04 フクダ電子株式会社 超音波探触子
DE69416926D1 (de) * 1993-08-13 1999-04-15 Sun Microsystems Inc Verfahren und Einrichtung zum Generieren von Animation mit hoher Geschwindigkeit mittels eines drei Bereiche umfassenden Pufferspeichers und assoziierten Bereichszeigern
US6026455A (en) * 1994-02-24 2000-02-15 Intel Corporation Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
US5752266A (en) * 1995-03-13 1998-05-12 Fujitsu Limited Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method
US5767866A (en) * 1995-06-07 1998-06-16 Seiko Epson Corporation Computer system with efficient DRAM access
US6070205A (en) * 1997-02-17 2000-05-30 Ssd Company Limited High-speed processor system having bus arbitration mechanism
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US5884051A (en) * 1997-06-13 1999-03-16 International Business Machines Corporation System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities
US6034542A (en) * 1997-10-14 2000-03-07 Xilinx, Inc. Bus structure for modularized chip with FPGA modules
US6240475B1 (en) * 1997-12-30 2001-05-29 Adaptec, Inc. Timer based arbitrations scheme for a PCI multi-function device
JP2000040061A (ja) * 1998-05-20 2000-02-08 Oki Data Corp バス使用権調停システム
JP2001184300A (ja) * 1999-12-27 2001-07-06 Hitachi Ltd データ処理プロセッサ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7231477B2 (en) 2003-03-19 2007-06-12 Matsushita Electric Industrial Co., Ltd. Bus controller
JP2007164428A (ja) * 2005-12-13 2007-06-28 Oki Electric Ind Co Ltd バス調停回路及びそれを用いたマルチレイヤバスシステム

Also Published As

Publication number Publication date
US20010005869A1 (en) 2001-06-28
US20040073731A1 (en) 2004-04-15
US6944696B2 (en) 2005-09-13
US6658511B2 (en) 2003-12-02

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