JP2001144213A - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置

Info

Publication number
JP2001144213A
JP2001144213A JP32515999A JP32515999A JP2001144213A JP 2001144213 A JP2001144213 A JP 2001144213A JP 32515999 A JP32515999 A JP 32515999A JP 32515999 A JP32515999 A JP 32515999A JP 2001144213 A JP2001144213 A JP 2001144213A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor device
forming
chip
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32515999A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001144213A5 (enExample
Inventor
Yuji Hara
雄次 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP32515999A priority Critical patent/JP2001144213A/ja
Publication of JP2001144213A publication Critical patent/JP2001144213A/ja
Publication of JP2001144213A5 publication Critical patent/JP2001144213A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
JP32515999A 1999-11-16 1999-11-16 半導体装置の製造方法および半導体装置 Pending JP2001144213A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32515999A JP2001144213A (ja) 1999-11-16 1999-11-16 半導体装置の製造方法および半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32515999A JP2001144213A (ja) 1999-11-16 1999-11-16 半導体装置の製造方法および半導体装置

Publications (2)

Publication Number Publication Date
JP2001144213A true JP2001144213A (ja) 2001-05-25
JP2001144213A5 JP2001144213A5 (enExample) 2005-06-30

Family

ID=18173690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32515999A Pending JP2001144213A (ja) 1999-11-16 1999-11-16 半導体装置の製造方法および半導体装置

Country Status (1)

Country Link
JP (1) JP2001144213A (enExample)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368160A (ja) * 2001-05-31 2002-12-20 Samsung Electronics Co Ltd ウェーハレベルパッケージ及びその製造方法
JP2003007929A (ja) * 2001-06-27 2003-01-10 Nichia Chem Ind Ltd 半導体チップとその製造方法
JP2005175327A (ja) * 2003-12-15 2005-06-30 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2006019636A (ja) * 2004-07-05 2006-01-19 Renesas Technology Corp 半導体装置
JP2006032598A (ja) * 2004-07-15 2006-02-02 Renesas Technology Corp 半導体装置の製造方法および半導体装置
WO2006059589A1 (ja) * 2004-11-30 2006-06-08 Kyushu Institute Of Technology パッケージングされた積層型半導体装置及びその製造方法
JP2006156926A (ja) * 2004-08-19 2006-06-15 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
JP2007114126A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置及びその製造方法
JP2007234881A (ja) * 2006-03-01 2007-09-13 Oki Electric Ind Co Ltd 半導体チップを積層した半導体装置及びその製造方法
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US7368815B2 (en) 2002-04-18 2008-05-06 Oki Electric Industry Co., Ltd. Semiconductor device which prevents light from entering therein
JP2008244383A (ja) * 2007-03-29 2008-10-09 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2008306071A (ja) * 2007-06-08 2008-12-18 Nec Corp 半導体装置及びその製造方法
JP2009176978A (ja) * 2008-01-25 2009-08-06 Rohm Co Ltd 半導体装置
JP2010062176A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置およびその製造方法
US8749065B2 (en) 2007-01-25 2014-06-10 Tera Probe, Inc. Semiconductor device comprising electromigration prevention film and manufacturing method thereof
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same
JP2016518730A (ja) * 2013-05-20 2016-06-23 クアルコム，インコーポレイテッド 上面および側壁保護のためのモールドを備える半導体デバイス
WO2016189986A1 (ja) * 2015-05-25 2016-12-01 リンテック株式会社 半導体装置の製造方法

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368160A (ja) * 2001-05-31 2002-12-20 Samsung Electronics Co Ltd ウェーハレベルパッケージ及びその製造方法
JP2003007929A (ja) * 2001-06-27 2003-01-10 Nichia Chem Ind Ltd 半導体チップとその製造方法
US7368815B2 (en) 2002-04-18 2008-05-06 Oki Electric Industry Co., Ltd. Semiconductor device which prevents light from entering therein
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
JP2005175327A (ja) * 2003-12-15 2005-06-30 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2006019636A (ja) * 2004-07-05 2006-01-19 Renesas Technology Corp 半導体装置
JP2006032598A (ja) * 2004-07-15 2006-02-02 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2006156926A (ja) * 2004-08-19 2006-06-15 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
US7576413B2 (en) 2004-11-30 2009-08-18 Kyushu Institute Of Technology Packaged stacked semiconductor device and method for manufacturing the same
WO2006059589A1 (ja) * 2004-11-30 2006-06-08 Kyushu Institute Of Technology パッケージングされた積層型半導体装置及びその製造方法
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same
JP2007114126A (ja) * 2005-10-21 2007-05-10 Fujitsu Ltd 半導体装置及びその製造方法
JP2007234881A (ja) * 2006-03-01 2007-09-13 Oki Electric Ind Co Ltd 半導体チップを積層した半導体装置及びその製造方法
US8749065B2 (en) 2007-01-25 2014-06-10 Tera Probe, Inc. Semiconductor device comprising electromigration prevention film and manufacturing method thereof
JP2008244383A (ja) * 2007-03-29 2008-10-09 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2008306071A (ja) * 2007-06-08 2008-12-18 Nec Corp 半導体装置及びその製造方法
US8975150B2 (en) 2007-06-08 2015-03-10 Renesas Electronics Corporation Semiconductor device manufacturing method
JP2009176978A (ja) * 2008-01-25 2009-08-06 Rohm Co Ltd 半導体装置
JP2010062176A (ja) * 2008-09-01 2010-03-18 Casio Comput Co Ltd 半導体装置およびその製造方法
US10141202B2 (en) 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
JP2016518730A (ja) * 2013-05-20 2016-06-23 クアルコム，インコーポレイテッド 上面および側壁保護のためのモールドを備える半導体デバイス
EP3000128B1 (en) * 2013-05-20 2020-07-01 Qualcomm Incorporated Semiconductor device comprising molding layer for top side and sidewall protection
WO2016189986A1 (ja) * 2015-05-25 2016-12-01 リンテック株式会社 半導体装置の製造方法
CN107615453A (zh) * 2015-05-25 2018-01-19 琳得科株式会社 半导体装置的制造方法
KR20180010194A (ko) * 2015-05-25 2018-01-30 린텍 가부시키가이샤 반도체 장치의 제조 방법
JPWO2016189986A1 (ja) * 2015-05-25 2018-03-15 リンテック株式会社 半導体装置の製造方法
CN107615453B (zh) * 2015-05-25 2020-09-01 琳得科株式会社 半导体装置的制造方法
KR102528047B1 (ko) 2015-05-25 2023-05-02 린텍 가부시키가이샤 반도체 장치의 제조 방법

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