JP2001144125A - 半導体装置および半導体装置の形成方法 - Google Patents

半導体装置および半導体装置の形成方法

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Publication number
JP2001144125A
JP2001144125A JP32015999A JP32015999A JP2001144125A JP 2001144125 A JP2001144125 A JP 2001144125A JP 32015999 A JP32015999 A JP 32015999A JP 32015999 A JP32015999 A JP 32015999A JP 2001144125 A JP2001144125 A JP 2001144125A
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Japan
Prior art keywords
bump
semiconductor device
protective material
package
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32015999A
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English (en)
Other versions
JP3672297B2 (ja
Inventor
Takashi Hosaka
俊 保坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
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Seiko Instruments Inc
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Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP32015999A priority Critical patent/JP3672297B2/ja
Priority to US09/639,709 priority patent/US6475897B1/en
Publication of JP2001144125A publication Critical patent/JP2001144125A/ja
Application granted granted Critical
Publication of JP3672297B2 publication Critical patent/JP3672297B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 ＩＣチップと同じ大きで高品質のＩＣパッケ
ージを安価な製造方法で提供する。 【解決手段】 半導体素子が形成されている半導体基板
の電極パッドに凸形バンプが接着しており、凸型バンプ
の柱部分と水平部分の一部が露出し他の部分は保護材料
でおおわれているＩＣパッケージである半導体装置とこ
の半導体装置を製造する方法。すなわち、保護材料の柱
部分の窓をあける時に、マスク材料を用いて、窓を写真
食刻法でパターニングし、保護材料をエッチング除去し
て行う。

Description

【発明の詳細な説明】
【発明の属する技術分野】本発明はＩＣチップと同じ大
きさの、いわゆるチップサイズパッケージの構造とその
製造方法に関する。
【従来の技術】これまでに作成されているチップサイズ
パッケージと呼ばれるものは、ＩＣチップを一個に分離
してからＩＣパッケージを作成していた。
【発明が解決しようとする課題】ＩＣパッケージの中に
ＩＣを入れるためには、かなりの余裕度を取らねばなら
ず、チップサイズパッケージといいながら、実際のサイ
ズはＩＣチップよりかなり大きくなっていた。また、Ｉ
Ｃパッケージ製造の工程が複雑で長いため費用がかか
り、かつ作成期間が長かった。
【課題を解決するための手段】上記の問題点を解決する
ために、本発明はウエハ状態でＩＣパッケージを作成
し、ＩＣチップと同じ大きさのＩＣパッケージを提供す
る。すなわち、ウエハ状態で電極パッドにバンプを接着
した後で、保護材料を塗布しマスク方法にてバンプ部分
を露出させる。その後、スクライブラインでウエハを切
断しＩＣパッケージを完成させる。
【実施例】本発明は、集積回路（ＩＣ）チップと同じ大
きさのＩＣパッケージを提供する技術に関するものであ
る。以下にこの発明の実施例を図面に基づいて説明す
る。図１は、ウエハサイズで形成された本発明の構造を
示すＩＣパッケージの断面図を示す。半導体基板１の表
面に電極パッド２が形成されている。また、半導体基板
１の表面は保護膜３でおおわれている。半導体基板内に
は集積回路が形成されている。図１では半導体基板内の
集積回路は省略する。以上のようにしてＩＣチップが構
成される。本発明は、このＩＣチップの電極パッド２に
バンプ４が接着している。バンプ４の形状は図１に示す
ように凸形をしている。ＩＣチップの表面は保護材料５
で覆われている。バンプ４の凸形部分の柱状部分４ａは
露出しており、外部電極との接点となる。保護材料５は
バンプ４の凸形部分の水平部分４ｂで切れている。以上
のようなＩＣパッケージは次のような特徴がある。 （１）ＩＣチップと同じ大きさである。 （２）ＩＣチップは完全に保護材料５でおおわれてい
る。この事により、ＩＣチップへの外部環境からの異物
の浸入は阻止されている。たとえば、外部の水分の浸入
はないため、ＩＣチップの水分による問題、たとえば電
極パッドの腐食は発生しない。 （３）バンプ４の柱部分４ａは保護材料５より突出して
いるため、外部電極との接続が容易である。この事を図
２により説明する。図２(ａ)は、図１のウエハサイズで
形成されたＩＣパッケージの集合体を個片にした状態の
１個のＩＣパッケージの断面構造図である。図２(ｂ)
は、図２(ａ)のＩＣパッケージを実装基板に取付けた状
態を示す。実装基板１６の表面に配線１７が形成されて
いる。配線１７とバンプ１４の柱部分１４ａが接着して
いる。バンプ１４の柱部分１４ａが保護材料１５より突
出しているため、外部配線１７との接続が容易となる。 （４）保護材料５はＩＣチップを強固に保持しているた
め、ＩＣパッケージの強度はＩＣチップ単体の強度に比
較し格段に向上している。 （５）構造が簡単なため、材料費を含めた製造コストが
非常に安い。以上のように、本発明によるＩＣパッケー
ジはチップサイズパッケージとして使用できる。 次に、本発明のＩＣパッケージの製造方法について詳細
に述べる。図３(ａ)は、ＩＣチップがまだ切断されてい
ない段階のウエハ状態を示す図である。ウエハ内には多
数のＩＣが存在する。半導体基板２１内には半導体素子
が多数形成されている。図中、半導体基板２１は、シリ
コン(Ｓｉ)半導体やガリウムひ素などの化合物半導体、
あるいは他の半導体である。電極パッド２２の材料は、
アルミニウム(Ａｌ)やアルミニウムの合金や不純物元素
の入ったアルミニウム、あるいは銅(Ｃｕ)が銅の合金や
不純物の入った銅、あるいは他の金属などである。 保
護膜２３の材料は、シリコン酸化膜（ＳｉＯ２）やシリ
コン窒化膜（ＳｉＮｘ）やポリイミド膜、あるいは他の
絶縁膜などである。次に図３(ｂ)に示すように、図１で
示されたＩＣが多数形成されたウエハ状態のままで、電
極パッド２２にバンプ２４を接着する。図３(ｃ)は、図
３(ｂ)の電極パッド２２の周辺を拡大した図である。バ
ンプ２４の形状は図３(ｃ)に示すように凸形の形状をな
るように形成する。バンプ２４の形成方法の１つとし
て、ワイヤボンダー装置を用いる方法がある。その方法
を図７、図８を用いて説明する。図７(ａ)において、金
属線３４の先にワイヤボンディング装置で丸い金属ボー
ル３５を形成する。次に図７(ｂ)に示すように、金属ボ
ール３５をＩＣの電極パッド ３２に押し付け、熱圧着
か超音波圧着などの方法により、金属ボール３５とＩＣ
の電極パッド３２を接着する。次に図８に示すように、
金属線３４を適当な長さの所３４ａで切断して、バンプ
３６とバンプ柱部分３６ａを形成する。以上の事をウエ
ハレベルで行うのであるが、ウエハサイズで見れば、バ
ンプ３６の高さはばらつきがあるので全体の高さをそろ
えるために、図８の工程の後でベベリングという工程を
加える事もある。金属線３４、金属ボール３５、バンプ
３６の材料として、金(Ａｕ)、パラジウム(Ｐｄ)、アル
ミニウム(Ａｌ)、銀(Ａｇ)、 鉛(Ｐｂ)と錫(Ｓｎ)の
半田合金、銀(Ag)と錫(Ｓｎ)の合金、その他の金属など
がある。次に図４(ａ)に示すように、保護材料２５を付
着する。図４(ｂ)は、図４(ａ)のバンプ２４の周辺を拡
大した図である。保護材料２５は、液体状の材料でウエ
ハ全体に塗布する事ができる。塗布する時の液体状の保
護材料２５の厚みは、最終的な厚みを考慮して決定しな
ければならない。すなわちバンプ２４の柱２４ａの先よ
り、保護材料２５の上面が最終的に上にならないよう
に、塗布する時の液体状の保護材料２５の厚みを調整す
る。そして、塗布した後で適当な温度でベークして液体
状の保護材料２５を固形化する。次に図５(ａ)に示すよ
うに、感光性材料のフォトレジストなどの材料を塗布
し、写真食刻法を用いマスク２６を作成する。次に図５
(ｂ)に示すように、マスク２６に沿って保護材料２５を
除去する。図５(ｃ)は、図５(ｂ)のバンプ２４の周辺部
分を拡大した図である。マスク２６は、バンプ２４の柱
部分２４ａを露出させ、かつバンプ２４の水平部分２４
ｂの所で切れるようにする。保護材料２５を除去する方
法として、マスク２６をエッチングしにくく、保護材料
２５をエッチングしやすいエッチング方法を用いればよ
い。あるいは、乾式エッチング方法を用いて、マスク２
６のパターンがあいている所から保護材料２５をエッチ
ング除去しても良い。さらにまた、ウエハをICパッケー
ジ毎に切断する時のためにウエハ内のスクライブライン
の保護材料２５も除去しておく事が望ましい。この時、
スクライブライン部分のマスク２６は前もって開いてい
る。次に図６(ａ)に示すように、マスク２６を取り除
く。図６(ｂ)は、図６(ａ)のバンプ２４の周辺部分を拡
大した図である。バンプ２４の柱部分２４ａと水平部分
２４ｂの一部は露出した状態にある。この状態のウエハ
を高温でアニールする事により、保護材料２５はより安
定した保護材料となり、ＩＣを機械的・化学的に強化す
る。これでウエハの中に多数のＩＣパッケージが完成し
たわけであるが、次にこれらをひとつひとつ分離する工
程について述べる。すなわち、図６(ａ)において、ウエ
ハ内のスクライブライン２７に沿って、ダイシング装置
を用いて切断し、ＩＣパッケージを分離する。このＩＣ
パッケージの切断の時に、切断すべきウエハ内の場所、
すなわちスクライブライン２７の所の保護材料２５を前
もって除去しておけば、比較的簡単にスクライブライン
２７に沿って切断できる。次に、バンプの高さ、保護材
料の厚さについて述べる。これらは、ＩＣパッケージの
使用環境によって異なる。図９において、電極パッド５
２の開口部の大きさをａ、電極パッド５２の部分の保護
膜５３の厚みをｂ、バンプ５４の平坦部分５４ｂの高さ
をｃ、バンプ５４の平坦部分５４ｂの大きさをｄ、バン
プ５４の柱部分５４ａの高さをｅ、柱部分５４ａの大き
さをｆ、保護材料５５の厚みをｇとする。バンプ５４の
平坦部分５４ｂの大きさｄは、一般的には電極パッド５
２の開口部の大きさａより小さい。ただし、バンプ５４
が電極パッド５２を完全に被うことができれば、ｄはａ
より大きくても良い。バンプ５４の柱部分５４ａの大き
さｆは、バンプの５４の平坦部分５４ｂの大きさｄより
小さい。保護材料５５の開口部とバンプ柱部分との距離
ｈは限りなくゼロで良いが、バンプ５４の柱部分５４ａ
にかぶると外部配線との接続不良を起こす恐れがあるの
で、マスクの合わせ余裕度とバンプ５４の位置の精度と
保護材料のエッチング精度とサイドエッチ量などを考え
て値を決める必要がある。バンプ５４の平坦部分５４ｂ
の端と保護材料55の開口部との距離ｉも原理的にはゼロ
で良いが、この部分からの水分など外部環境の異物が浸
入する可能性が最も大きいので、保護材料５５はバンプ
５４の平坦部分５４ｂに確実にかかっている必要があ
る。たとえばバンプ５４の位置精度がｘミクロンｍ、マ
スクの合わせ誤差ｙミクロンｍ、保護材料５５のエッチ
ングの精度ｚミクロンｍ、サイドエッチ量ｗミクロンｍ
とするとｉはｘ＋ｙ＋ｚ＋ｗより大きくなければならな
い。バンプ５４の柱部分５４ａの大きさｆは、ワイヤボ
ンディングで形成する場合は、金属線の太さで決まる。
このｆは、外部配線と接続するので、その点からの設計
も必要となる。次にバンプ５４の平坦部分５４ｂの高さ
ｃは、ＩＣパッケージをどの程度の強度を持たせるか、
どの程度の信頼性を要求するかで決定される。一般的に
は１０ミクロンｍ〜５０ミクロンｍあれば良い。また、
バンプ５４の柱部分５４ａの高さｅは、保護材料５５の
厚みｇからｃを引いた値より大きくし、保護材料５５よ
り上にバンプの頭を出す必要がある。どのくらい頭を出
すかは、このＩＣパッケージを実装する技術によるが、
１０ミクロンｍ以上出しておけば実装側からは安全であ
ろう。保護材料の厚みｇは、バンプ５４の平坦部分５４
ｂをおおうのでｃよりは大きくなければならない。一般
的には、ｇは１２ミクロンｍ〜７０ミクロンｍとする。
尚、図５、図６では、水平部分に保護材料の端が来るよ
うにしたが、マスクおよびエッチング条件を選ぶことに
より、バンプの柱部分だけを露出するようにできること
はいうまでもない。
【発明の効果】以上、説明したようにウエハ状態でＩＣ
パッケージを作成するので、工程がかなり少なくなり大
幅な費用削減と大幅な納期短縮ができる。また、凸形バ
ンプを使用し保護材料がバンプの水平部分をおおってい
るので、信頼性と品質が非常に高い。
【図面の簡単な説明】
【図１】本発明の半導体装置であるウエハサイズのＩＣ
パッケージの構造を示す図である。
【図２】本発明の半導体装置を実装状態を示す図であ
る。
【図３】本発明の半導体装置の製造方法を示す図であ
る。
【図４】本発明の半導体装置の製造方法を示す図であ
る。
【図５】本発明の半導体装置の製造方法を示す図であ
る。
【図６】本発明の半導体装置の製造方法を示す図であ
る。
【図７】本発明の半導体装置に用いるバンプを作成する
方法を示す図である。
【図８】本発明の半導体装置に用いるバンプを作成する
方法を示す図である。
【図９】本発明の半導体装置の寸法を説明する図であ
る。
【符号の説明】
１、１１、２１、３１、５１ 半導体基板 ２、１２、２２、３２、５２ 電極パッド ３、１３、２３、３３、５３ 保護膜 ４、１４、２４、３６、５４ バンプ ５、１５、２５、５５ 保護材料 ４ａ、１４ａ、２４ａ、５４ａ バンプの柱部分

Claims (7)

    【特許請求の範囲】
  1. 【請求項１】 半導体素子が形成されている半導体基板
    の電極パッドに凸形バンプが接着しており、凸形バンプ
    の水平部分の一部と柱部分が露出し他の部分は保護材料
    でおおわれている半導体装置。
  2. 【請求項２】 凸形バンプ柱部分は保護材料より飛び出
    している請求項１記載の半導体装置。
  3. 【請求項３】 半導体素子が形成されている半導体基板
    の電極パッドに凸形バンプが接着しており、凸形バンプ
    の柱部分が露出し他の部分は保護材料でおおわれている
    半導体装置。
  4. 【請求項４】 半導体基板の中に半導体素子を形成した
    後に、半導体素子の電極パッドにバンプを接着する工程
    と半導体素子を保護する材料を塗布する工程と、前記バ
    ンプの水平部分の一部と柱部分を露出する工程とを含む
    請求項１および請求項２記載の半導体装置の製造方法。
  5. 【請求項５】 半導体基板の中に半導体素子を形成した
    後に、半導体素子の電極パッドにバンプを接着する工程
    と半導体素子を保護する材料を塗布する工程と前記バン
    プの柱部分を露出する工程とを含む請求項３記載の半導
    体装置の製造方法。
  6. 【請求項６】 凸形バンプはワイヤボンディング装置を
    用いて形成する請求項４および請求項５記載の半導体装
    置の製造方法。
  7. 【請求項７】 半導体基板の中に半導体素子を形成した
    後に、半導体素子の電極パッドにバンプを接着する工程
    と半導体素子を保護する感光性の材料を塗布する工程と
    写真食刻法を用い前記バンプの柱部分を露出する工程と
    を含む請求項２、請求項３、および請求項５記載の半導
    体装置の製造方法。
JP32015999A 1999-11-10 1999-11-10 半導体装置の製造方法 Expired - Fee Related JP3672297B2 (ja)

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3459223B2 (ja) * 2000-04-19 2003-10-20 沖電気工業株式会社 半導体装置及びその製造方法
US6940178B2 (en) * 2001-02-27 2005-09-06 Chippac, Inc. Self-coplanarity bumping shape for flip chip
US20040130034A1 (en) * 2001-06-13 2004-07-08 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package
TW533556B (en) * 2002-02-21 2003-05-21 Advanced Semiconductor Eng Manufacturing process of bump
JP3949505B2 (ja) * 2002-04-26 2007-07-25 シャープ株式会社 接続端子及びその製造方法並びに半導体装置及びその製造方法
TWI232569B (en) * 2003-03-21 2005-05-11 Comchip Technology Co Ltd Metal bonding method for semiconductor circuit components employing prescribed feeds of metal balls
JP4627632B2 (ja) * 2004-05-17 2011-02-09 Ｏｋｉセミコンダクタ株式会社 半導体装置
US7375431B1 (en) * 2005-03-18 2008-05-20 National Semiconductor Corporation Solder bump formation in electronics packaging
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US20080280393A1 (en) * 2007-05-09 2008-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming package structures
US7772106B2 (en) * 2007-11-07 2010-08-10 Stats Chippac, Ltd. Method of forming an inductor on a semiconductor wafer
JP2009130271A (ja) * 2007-11-27 2009-06-11 Panasonic Corp 半導体装置とその製造方法
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US20170352639A1 (en) * 2016-06-02 2017-12-07 Knowles Electronics, Llc Method for protecting bond pads from corrosion

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281435A (ja) * 1986-05-30 1987-12-07 Hitachi Ltd 半導体装置
US5444300A (en) * 1991-08-09 1995-08-22 Sharp Kabushiki Kaisha Semiconductor apparatus with heat sink
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
JPH07201864A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 突起電極形成方法
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP3146345B2 (ja) * 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
KR100186333B1 (ko) * 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법

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