JP2001015698A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

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Publication number
JP2001015698A
JP2001015698A JP11188753A JP18875399A JP2001015698A JP 2001015698 A JP2001015698 A JP 2001015698A JP 11188753 A JP11188753 A JP 11188753A JP 18875399 A JP18875399 A JP 18875399A JP 2001015698 A JP2001015698 A JP 2001015698A
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film
silicon nitride
capacitor
forming
insulating film
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JP3252835B2 (ja
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Takumi Mikawa
巧 三河
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Panasonic Holdings Corp
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Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
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Abstract

(57)【要約】 【課題】 保護膜として耐湿性に優れたシリコン窒化膜
を使用しながらも、強誘電体薄膜を容量絶縁膜とする容
量素子を内蔵し、なおかつ強誘電体特性の劣化のない半
導体装置およびその製造方法を提供することを目的とす
る。 【解決手段】 シリコン基板１上に形成された強誘電体
膜を容量絶縁膜３とする強誘電体キャパシタ領域１３を
含む半導体装置を被覆して層間絶縁膜５が形成されてお
り、かつその上に形成された配線層１４を覆って、窒素
とシランガスのみを使用した電気化学反応性化学気相成
長法（ECR-CVD法）で成膜された、膜中の水素の結合状
態がSi-H結合ではなくN-H結合の状態で含まれているこ
とを特徴としたシリコン窒化膜からなる保護膜１５を形
成することにより、水素の拡散による容量絶縁膜３の劣
化を防ぐことができる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、強誘電体を容量絶
縁膜とする容量素子を備えた半導体装置およびその製造
方法に関するものである。
【０００２】
【従来の技術】近年、マイクロコンピュータ等の高速
化、低消費電力化が進む中で民生用電子機器が一段と高
度化し、そこに使用される半導体装置の半導体素子の微
細化が急速に進められてきている。それに伴って電子機
器から発生する電磁波雑音である不要輻射が大きな問題
になり、この不要輻射低減対策として高誘電率を有する
誘電体（以下単に高誘電体という）を容量絶縁膜とする
大容量の容量素子を半導体集積回路装置等に内蔵する技
術が注目を浴びている。またダイナミックＲＡＭの高集
積化に伴い、容量絶縁膜として従来用いられてきた珪素
酸化物または珪素窒化物に代わって高誘電体を用いる技
術が広く研究されている。さらに低動作電圧かつ高速書
込み・高速読出しが可能な不揮発性ＲＡＭの実用化を実
現するために、自発分極特性を有する強誘電体膜に関す
る研究開発が盛んに行われている。
【０００３】これらの半導体装置を実現するための最重
要課題は、容量素子の特性を劣化させることなく集積化
を実現するための構造およびその製造方法を開発するこ
とにある。特に強誘電体材料は酸素原子を持つ層状酸化
物であることから、水素雰囲気中で容易に還元され、容
易に強誘電体特性の劣化を引き起こす。この強誘電体材
料を半導体メモリの容量絶縁膜として使用する場合、成
膜の際に高いエネルギーを持つ水素原子が生成される保
護膜形成工程などの水素あるいは還元性雰囲気に留意し
て、耐還元性に強いプロセスを構築することが重要であ
る。特に保護膜などに適用されるシリコン窒化膜中には
水素原子が十分含有されているので、形成後の熱処理は
厳禁であるとともに、その水素の含有量から成膜時にど
れだけの水素が発生しているかの指標となっていた。
【０００４】以下、従来の半導体装置およびその製造方
法について、図面を参照しながら説明する。
【０００５】図９は従来の半導体装置の要部断面図であ
る。図９において、１は基板、２は白金膜からなる下電
極、３は強誘電体膜からなる容量絶縁膜、４は白金膜か
らなる上電極、５はシリコン酸化膜、シリコン窒化膜等
からなる層間絶縁膜で、その層間絶縁膜５には上電極４
および下電極２の上面の一部にそれぞれ達するコンタク
トホール６ａおよび６ｂが形成されている。７ａ、７ｂ
は窒化チタン、アルミニウム等の導電物質からなる配線
層である。８はそれらをすべて被覆するように形成され
たシリコン窒化膜からなる保護膜である。ここで保護膜
は窒素、シラン及びアンモニアを使用した標準的なプラ
ズマ化学気相成長法により成膜されており、通常その膜
中にはシリコンと水素が結合する形のSi-H結合として水
素は１０の２２〜２３乗個/cm3程度含有されており、強
誘電体特性の劣化の原因となっている。
【０００６】図１０（ａ）〜（ｆ）は従来の容量素子の
製造方法を説明する工程断面図であり、図１０（ａ）に
示すように、絶縁性基板１の上に第１の白金膜９、強誘
電体膜１０および第２の白金膜１１が順次形成される。
次に図１０（ｂ）に示すように、第２の白金膜１１が選
択的にエッチングされて上電極４が形成される。つぎに
図１０（ｃ）に見られるように強誘電体膜１０および第
１の白金膜９が選択的にエッチングされて容量絶縁膜３
および下電極２が形成される。さらに下電極２との接続
を図るためのコンタクトホールが形成される領域の強誘
電体膜１０が選択的にエッチングされる。次に図１０
（ｄ）に示すように、絶縁膜５が形成され、さらに絶縁
膜５に下電極２および上電極４の上面に達するコンタク
トホール６ａおよび６ｂがそれぞれ形成され、次に図１
０（ｅ）に示すように、チタン膜および窒化チタン膜か
らなる配線層７ａ、７ｂが形成される。最後に図１０
（ｆ）に示すように標準的なプラズマCVD法にて成膜し
たシリコン窒化膜からなる保護膜８が形成される。更に
図１０では図示は省略したが、通常は電極配線の外部接
続する領域の保護膜に開口部を設けてボンディングパッ
ドが形成されて一連の製造工程が終了する。
【０００７】
【発明が解決しようとする課題】しかしながら上記従来
の構成を有する半導体装置では、水分の浸入によるMOS
トランジスタや強誘電体からなる容量素子の特性劣化を
防ぐために、保護膜として耐湿性に優れたシリコン窒化
膜を形成するが、通常高周波プラズマCVDでシリコン窒
化膜を形成する際には、原料ガスとしてSiH4及びNH3を
用いるために、その膜中にはSi-H結合が１０の２２〜２
３乗個/cm3程度含有されている。このSi-H結合の水素
が、後の熱処理で容易に結合が切れて強誘電体膜まで拡
散し、層状酸化物を呈する強誘電体結晶から酸素を脱離
し、強誘電体の分極特性を劣化させる。強誘電体特性と
Si-H結合の関係を図１１に示す。強誘電体メモリデバイ
スの動作に必要な分極量を得るためには、半導体製造工
程中の熱処理がある場合には、Si-H結合が１０の２１乗
個/cm3以下に抑え込むことが必要とされることが明らか
である。仮に後工程の熱処理がすべて無くしたとして
も、強誘電体メモリのデータリテンション信頼性を高温
で保証するためには少しでもSi-H結合を抑えることが重
要である。
【０００８】本発明は上記課題を解決するものであり、
保護膜としての優れた耐湿性を維持しながら、膜中のSi
-H結合を１０の２１乗個/cm3以下に抑え込み、強誘電体
からなる容量素子の分極特性の劣化を防ぎ、また強誘電
体メモリとしての高温でのデータリテンション信頼性を
保証することを可能にする半導体装置およびその製造方
法を提供することを目的とする。
【０００９】
【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置は、下電極、強誘電体膜からなる
容量絶縁膜、及び上電極で構成された容量素子を被覆し
て形成された層間絶縁膜と、更にその上に形成された電
極配線とを被覆して窒素とシランガスを材料ガスとして
使用した電子サイクロトロン共鳴化学気相堆積法(以
下、ECR-CVD法と略す）を用いて保護膜となるシリコン
窒化膜を形成したことを特徴としたものである。ECR-CV
D法とは、成膜時に800W以上の電力をかけ高密度プラズ
マを発生させ、通常のプラズマCVD(電力は500W以下)で
は分解しにくい窒素を分解、シランガスと反応させ、反
応を促進するためのアンモニアを使用せずにシリコン窒
化膜を形成するもので、水素をほとんどN-H結合の形で
取り込むことを特徴としたものである。これにより、保
護膜のシリコン窒化膜中の結合力の弱いSi-H結合として
の水素原子含有量を１０の２１乗個/cm3以下に抑え込み
（N-H結合の水素は結合力が強いために拡散しない）、
保護膜としての優れた耐湿性を維持しながら、水素が強
誘電体膜に拡散した際に引き起こす強誘電体結晶への還
元作用（酸素欠損）による分極特性の劣化を防止するよ
うにしたものである。
【００１０】本発明の第１の作用は、基板と、その基板
の一表面上に形成された下電極とその下電極の表面に形
成された強誘電体膜よりなる容量絶縁膜と、その容量絶
縁膜の表面に下電極と接触することなく形成された上電
極と、その上に形成された層間絶縁膜と、コンタクトホ
ールを介して上電極または下電極とそれぞれ電気的に接
続するように形成された配線層と、窒素とシランガスを
材料ガスとして使用したECR-CVD法を用いて、それらす
べてを被覆して形成して膜中のSi-H結合の含有量が１０
の２１乗個/cm3以下に抑え込むことを特徴としたシリコ
ン窒化膜を備える構成としたものであり、シリコン窒化
膜中から強誘電体膜への水素の拡散を低減することであ
る。
【００１１】本発明の他の作用は、窒素とシランガスを
材料ガスとして使用したECR-CVD法を用いて形成したN-H
結合が主成分結合であることの特徴を有するシリコン窒
化膜を強誘電体を含む容量素子にオーバーラップする領
域に形成し、それ以外の領域に窒素とシランガスとアン
モニアを材料ガスとして使用しプラズマ化学気相成長法
を用いて形成したSi-H結合が主成分結合であることを特
徴としたシリコン窒化膜で被覆する構成にしたものであ
り、強誘電体膜を含む容量素子への水素の拡散を防止し
つつ、それ以外のトランジスタ形成部などへは水素の拡
散を積極的に利用して、欠陥準位を水素によって回復
し、トランジスタ特性が回復することである。
【００１２】本発明の他の作用は、窒素とシランガスを
材料ガスとして使用したECR-CVD法を用いて形成したN-H
結合が主成分結合であることの特徴を有するシリコン窒
化膜を強誘電体を含む容量素子に少なくとも10μm以上
はみ出してオーバーラップさせる領域を含めて形成し、
それ以外の領域に窒素とシランガスとアンモニアを材料
ガスとして使用しプラズマ化学気相成長法を用いて形成
したSi-H結合が主成分結合であることを特徴としたシリ
コン窒化膜で被覆する構成にしたものであり、熱処理に
よる後者のシリコン窒化膜から強誘電体膜を含む容量素
子への水素の拡散を防止しつつ、それ以外のトランジス
タ形成部などへは水素の拡散を積極的に利用して、欠陥
準位を水素によって回復し、トランジスタ特性が回復す
ることである。
【００１３】
【発明の実施の形態】以下、本発明の一実施の形態にお
ける半導体装置について図面を参照しなが説明する。
【００１４】（実施の形態）図１は本発明の第１の実施
の形態における半導体装置の構造を示す断面図である。
図１において、１は基板、２は白金膜からなる下電極、
３は強誘電体膜からなる容量絶縁膜、４は白金膜からな
る上電極、５はシリコン酸化膜、シリコン窒化膜等から
なる層間絶縁膜で、その層間絶縁膜５には上電極４およ
び下電極２の上面の一部にそれぞれ達するコンタクトホ
ール６ａおよび６ｂが形成されている。１２はトランジ
スタ領域、１３は強誘電体キャパシタ領域、１４は配線
層である。１５はそれらをすべて被覆するように形成さ
れたシリコン窒化膜からなる保護膜である。ここで保護
膜はECR-CVD法により成膜されており、膜中のSi-H結合
の含有量が１０の２１乗個/cm3以下であることを特徴と
している。そのECR-CVD法により成膜したシリコン窒化
膜をサンプル１とし、比較として、通常のプラズマCVD
により成膜したシリコン窒化膜をサンプル２とし、強誘
電体膜からなる容量絶縁膜を有する容量素子に与える影
響について述べる。まず、それぞれの膜中のN-H結合とS
i-H結合の濃度の指標となるFTIR分析の結果について図
２に示す。この結果から形成方法により膜中のN-H結合
とSi-H結合の濃度を変更できることがわかり、サンプル
１では、Si-H結合の含有量が検出限界以下となるシリコ
ン窒化膜をECR-CVD法により実現できている。次にこれ
らの強誘電体メモリデバイスのリテンション特性につい
て図３に示す。この図は、リテンション加速試験を実施
したものであるが、デバイス動作１０年保証に相当する
100hでの相対読み出し電荷量では、サンプル１の方が大
きく、これを信頼性保証時間に換算すると、おおよそ５
倍ほど延長できることを意味し、信頼性特性で向上させ
る著しい効果が観測できる。
【００１５】上記実施の形態は、従来の半導体装置の製
造方法を示す断面図の図１０（f）における標準的なプ
ラズマCVD法にて成膜した保護膜８をECR-CVD法により形
成することにより実現できる。
【００１６】図４は本発明の第２の実施の形態における
半導体装置を説明する断面図であり、図５（ａ）〜
（ｄ）は本発明の第２の実施の形態における半導体装置
を製造するための製造方法の一実施を説明する工程断面
図である。図５(ａ)では、絶縁性基板１の上に、白金か
らなる下電極２と上電極４と強誘電体膜からなる容量絶
縁膜３によって形成された強誘電体容量素子とそれらを
絶縁膜５で被覆し、下電極２および上電極４の上面に達
するコンタクトホール６ａおよび６ｂがそれぞれ形成さ
れ、チタン膜および窒化チタン膜からなる配線層７ａ及
び７ｂが形成されている。次に図５(ｂ)に示すように窒
素とシランとアンモニアのガスによる通常のプラズマCV
D法により成膜した膜中のSi-H結合としての水素原子含
有量が１０の２２個/cm3以上であることを特徴としたシ
リコン窒化膜からなる保護膜８が形成される。次に図５
(ｃ)に示したように強誘電体容量素子に少なくともオー
バーラップする領域の前記保護膜８を選択的に除去す
る。最後に図５(ｄ)に示したように、窒素とシランのみ
のガスによるECR-CVD法により成膜した膜中のSi-H結合
の含有量が１０の２１乗個/cm3以下であることを特徴と
したシリコン窒化膜からなる保護膜１５を全体に形成
し、本発明の第２の実施の形態となる半導体装置を実現
できる。更に図５では図示は省略したが、通常は電極配
線の外部接続する領域の保護膜に開口部を設けてボンデ
ィングパッドが形成されて一連の製造工程が終了する。
図中の番号は図４及び図５にて共通である。
【００１７】この図４の構造をもつ半導体装置をサンプ
ル３とし、図中１５に従来のシリコン窒化膜を構造に持
つ半導体装置をサンプル４とし、特性の違いについて述
べる。まず、これらを４５０℃１時間窒素雰囲気中で熱
処理したときのヒステリシス特性を図６に示す。この温
度で熱処理すると、窒化膜中の水素が拡散し強誘電体薄
膜のペロブスカイト構造中の酸素を還元し結晶構造を破
壊するのが一般である。ところが、サンプル４では明ら
かにヒステリシス特性が劣化するとともにキャパシタも
ショートすることも合わせて観測されるが、サンプル３
では、キャパシタ耐圧も維持し、ヒステリシスはサンプ
ル４の２倍以上の値を保持し、強誘電体メモリのデバイ
ス動作に対しては十分な値を有している。以上の結果か
ら膜中のSi-H結合の含有量を抑える事により、たとえ熱
処理を行っても、その強誘電体特性の劣化を抑えること
ができる。
【００１８】また、このサンプル３におけるトランジス
タのしきい値の熱処理前後での分布を図７に示す。図７
に示したように、トランジスタの動作電圧（しきい値V
t）がアニール処理により、その値が減少し、ばらつき
も小さくなっていることがわかる。以上より強誘電体膜
への水素の拡散を防止した状態でトランジスタ特性を回
復させることを可能にしている。
【００１９】最後に図４に強誘電体領域と窒素とシラン
のみのガスによるECR-CVD法により成膜した膜中のSi-H
結合の含有量が１０の２１乗個/cm3以下であることを特
徴としたシリコン窒化膜からなる保護膜１５をキャパシ
タ層間膜５に接触してオーバーラップさせる領域をdと
定義したが、その領域とデータ保持後の強誘電体メモリ
の分極量の関係を図８に示す。この図から少なくとも10
μm以上はみ出してオーバーラップさせる領域を含めて
形成することにより、水素の拡散による強誘電体特性へ
の影響がなく、リテンション特性を維持できることがわ
かる。
【００２０】
【発明の効果】上記実施より明らかなように本発明は、
強誘電体膜よりなる容量絶縁膜を含む容量素子を被覆す
る保護膜を窒素とSiH4のみのガスによるECR-CVD法によ
り成膜することにより、保護膜中のSi-H結合の含有量を
１０の２１個/cm3以下に抑え込むことにより、水素の拡
散を低減し、水素の容量絶縁膜への拡散による容量素子
の電気的特性の劣化を防止することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態を示す断面図
【図２】窒化膜の吸収スペクトルを示す図
【図３】強誘電体メモリデバイスのリテンション特性を
示す図
【図４】本発明の第２の実施の形態を示す断面図
【図５】本発明の第２の実施の形態を示す工程断面図
【図６】強誘電体キャパシタのヒステリシス特性（水素
拡散による強誘電体特性の劣化）を示す図
【図７】トランジスタのしきい値Vt特性を示す図
【図８】シリコン窒化膜被覆領域と分極量との関係を示
す図
【図９】強誘電体膜からなる容量素子を含む半導体装置
の従来構造を示す断面図
【図１０】従来構造の半導体装置の製造方法を示す工程
図
【図１１】強誘電体特性の劣化を示す図
【符号の説明】
１ 基板 ２ 下電極 ３ 容量絶縁膜 ４ 上電極 ５ 層間絶縁膜 ６ａ 上電極へのコンタクトホール ６ｂ 下電極へのコンタクトホール ７ａ 上電極への配線層 ７ｂ 下電極への配線層 ８ 標準的なプラズマCVD法にて成膜したシリコン窒化
膜からなる保護膜 ９ 第１の白金膜 １０ 強誘電体膜 １１ 第２の白金膜 １２ トランジスタ領域 １３ 強誘電体キャパシタ領域 １４ 配線層 １５ ECR-CVD法にて成膜したシリコン窒化膜からなる
保護膜
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/8242

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】 基板上に少なくとも下電極、強誘電体膜
    からなる容量絶縁膜、及び上電極で構成された容量素子
    と、前記容量素子を被覆して形成された層間絶縁膜と、
    前記層間絶縁膜の上に形成された電極配線とそれを被覆
    して形成された保護膜とを有し、かつ前記保護膜はRF電
    力によって発生する高密度プラズマ状態下で窒素とシラ
    ンガスのみを使用した電子サイクロトロン共鳴化学気相
    堆積法(ECR-CVD法）で成膜されたシリコン窒化膜である
    ことを特徴とした半導体装置。
  2. 【請求項２】 ECR-CVD法で成膜されたシリコン窒化膜
    を、少なくとも下電極、強誘電体膜からなる容量絶縁
    膜、及び上電極で構成された容量素子にオーバーラップ
    する領域に形成し、前記容量素子にオーバーラップしな
    い領域は窒素とシランガスとアンモニアガスを使用した
    プラズマ化学気相成長法で成膜されたシリコン窒化膜で
    被覆することを特徴とする半導体装置。
  3. 【請求項３】 ECR-CVD法で成膜したシリコン窒化膜を
    前記容量素子にオーバーラップする領域に加え、その外
    側に少なくとも10μmはみ出した領域に形成し、前記容
    量素子及びその外側に10μmはみ出した領域にオーバー
    ラップしない領域に窒素とシランガスとアンモニアガス
    を使用したプラズマ化学気相成長法で成膜されたシリコ
    ン窒化膜で被覆することを特徴とする請求項２記載の半
    導体装置。
  4. 【請求項４】 基板に下電極、強誘電体膜からなる容量
    絶縁膜、及び上電極で構成された容量素子を形成する工
    程と、前記容量素子を覆って層間絶縁膜を形成する工程
    と、前記層間絶縁膜に開口部を形成する工程と、前記開
    口部を含んで電極配線を形成する工程と、前記電極配線
    を覆って、窒素とシランガスのみを使用したECR-CVD法
    でシリコン窒化膜を形成する工程とを有する半導体装置
    の製造方法。
  5. 【請求項５】 基板に下電極、強誘電体膜からなる容量
    絶縁膜、及び上電極で構成された容量素子を形成する工
    程と、前記容量素子を覆って層間絶縁膜を形成する工程
    と、前記層間絶縁膜に開口部を形成する工程と、前記開
    口部を含んで電極配線を形成する工程と、前記電極配線
    を覆って、前記容量素子に少なくともオーバーラップす
    る領域に窒素とシランガスのみを使用したECR-CVD法で
    シリコン窒化膜を形成する工程と、前記容量素子にオー
    バーラップしない領域に窒素とシランガスとアンモニア
    ガスを使用したプラズマ化学気相成長法でシリコン窒化
    膜を形成する工程と、その後熱処理を行う工程とを有す
    る半導体装置の製造方法。
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