JP2000505245A - 電子アセンブリの製造におけるひずみをできるだけ抑える方法 - Google Patents
電子アセンブリの製造におけるひずみをできるだけ抑える方法Info
- Publication number
- JP2000505245A JP2000505245A JP10521414A JP52141498A JP2000505245A JP 2000505245 A JP2000505245 A JP 2000505245A JP 10521414 A JP10521414 A JP 10521414A JP 52141498 A JP52141498 A JP 52141498A JP 2000505245 A JP2000505245 A JP 2000505245A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- layers
- dielectric
- conductive layer
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- FZHAPNGMFPVSLP-UHFFFAOYSA-N silanamine Chemical compound [SiH3]N FZHAPNGMFPVSLP-UHFFFAOYSA-N 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000000527 sonication Methods 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- ZNOCGWVLWPVKAO-UHFFFAOYSA-N trimethoxy(phenyl)silane Chemical compound CO[Si](OC)(OC)C1=CC=CC=C1 ZNOCGWVLWPVKAO-UHFFFAOYSA-N 0.000 description 1
- AATYKEFFPLPLST-UHFFFAOYSA-N trimethylsilylurea Chemical compound C[Si](C)(C)NC(N)=O AATYKEFFPLPLST-UHFFFAOYSA-N 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
- Y10T156/1092—All laminae planar and face to face
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.水平対称面に対称に複数の誘電性層と伝導性層を配置し、 水平対称面の外側に、他の層に比較して最大モジュラスと最小厚み公差を有す る層を選択的に配置し、 前記誘電性層と伝導性層をラミネートする、 各工程を含む、電子基材の製造におけるひずみをできるだけ抑える方法。 2.配置工程が、コア層の相対する側にそれぞれ第1誘電性層と第2誘電性層 を、第1誘電性層と第2誘電性層の反対側にそれぞれ第1伝導性層と第2伝導性 層を配置することを含む請求項1に記載の方法。 3.第1誘電性層と第2誘電性層がほぼ同じ厚みを有して同じ材料からなり、 第1伝導性層と第2伝導性層がほぼ同じ厚さを有して同じ材料からなり、第1伝 導性層と第2伝導性層が第1誘電性層と第2誘電性層より高いモジュラスとより 小さい厚み公差を有する請求項2に記載の方法。 4.配置工程が、第3誘電性層と第4誘電性層を第1伝導性層と第2伝導性層 のそれぞれ反対側に、第3伝導性層と第4伝導性層を第2誘電性層と第3誘電性 層のそれぞれ反対側に配置することを含む請求項3に記載の方法。 5.第3誘電性層と第4誘電性層がほぼ同じ厚みを有して同じ材料からなり、 第3伝導性層と第4伝導性層がほぼ同じ厚さを有して同じ材料からなり、第3伝 導性層と第4伝導性層が第3誘電性層と第4誘電性層より高いモジュラスとより 小さい厚み公差を有する請求項4に記載の方法。 6.第3誘電性層と第4誘電性層が第1誘電性層と第2誘電性層 より高いモジュラスを有する請求項5に記載の方法。 7.第3伝導性層と第4伝導性層が第1伝導性層と第2伝導性層よりも大きい 厚みを有する請求項5に記載の方法。 8.水平対称面に対称に配置された複数の誘電性層と伝導性層を備え、他の層 に比較して最大モジュラスと最小厚み公差を有する層が、水平対称面からみて外 側の方に選択的に配置された、ラミネート式基材。 9.複数の誘電性層と伝導性層が、コア層、及びコア層を通る水平対称面に対 称に配置されて積層に配置された、複数の交互に配置されて垂直に重ねられた誘 電性層と伝導性層を含み、 積層の最も外側の層は、実質的に同じ厚さを有する伝導性層であり、最も外側 の伝導性層の厚みが、コア層以外の他の伝導性層よりも厚い請求項8に記載のラ ミネート式構造。 10.誘電性層が、コア層の反対側にそれぞれ配置された第1誘電性層と第2 誘電性層を含み、第1誘電性層と第2誘電性層は、同じ材料からなって、ほぼ同 じ厚みと同じ厚み公差を有する請求項9に記載のラミネート式基材。 11.伝導性層が、誘電性層の反対側にそれぞれ配置された第1伝導性層と第 2伝導性層を含み、第1誘電性層と第2誘電性層が、同じ材料からなって、ほぼ 同じ厚みと同じ厚み公差を有し、第1伝導性層と第2伝導性層の厚み公差が、第 1誘電性層と第2誘電性層のそれよりも実質的に小さい請求項10に記載のラミ ネート式基材。 12.第1伝導性層と第2伝導性層の厚み公差が1μmであり、第1誘電性層 と第2誘電性層の厚みが6〜8μmである請求項11に記載のラミネート式基材 。 13.第1誘電性層と第2誘電性層の厚み公差が、厚みの約15 %である請求項12に記載のラミネート式基材。 14.伝導性層とコア層が銅からなり、誘電性層が、シアネートエステルエポ キシと粉末状セラミックフィラーを含浸された延伸膨張ポリテトラフルオロエチ レン(ePTFE)マトリックスからなる請求項10に記載のラミネート式基材 。 15.コア層を作成し、 コア層を通る対称面に対称に、コア層に対して垂直な重なりで、複数の交互に 配置された誘電性層と伝導性層を配置し、積層に配置し、 積層の最も外側の層に、実質的に同じ厚みを有する伝導性層を選択し、最も外 側の伝導性層の厚みが、コア層以外の他の伝導性層よりも厚い、 各工程を含む、電子パッケージの製造におけるひずみをできるだけ抑える方法 。 16.2つの面とその2つの面の間の対称面を有する金属系伝導性材料からな る中央に配置された層、 第1誘電性材料の2つの層であって、その誘電性材料の各層が、第1製造厚み 公差を有し、その対称面の反対側にあって互いに等距離にあり、その中央に配置 された層の各面を背にした第1誘電性材料の2つの層、 別な誘電性材料の2つの層であって、その別な誘電性材料のその層は、第1厚 み公差よりも小さい第2製造厚み公差を有し、対称面の反対側にあって互いにそ の第1誘電性材料から等距離にある別な誘電性材料の2つの層、及び 第1と第2の製造厚み公差より小さい第3製造厚み公差を有する金属系伝導性 材料の2つの層、 を備えたマイクロチップ用基材。 17.中央に配置された層が銅からなる請求項16に記載の基材。 18.誘電性材料の2つの層が、シアネートエステル/エポキシを含浸された 延伸膨張ポリテトラフルオロエチレンをさらに含む請求項17に記載の基材。 19.別な誘電体からなる2つの層が、ビスマレイミド−トリアジン(BT) −エポキシ/ガラスをさらに含む請求項16に記載の基材。 20.その金属系伝導性材料の2つの層が銅をさらに含む請求項16に記載の 基材。 21.第2の相対する層のペアを意図的に不均衡にすることによって相対する 層のペアの間に存在する曲げモーメントの不均衡を相殺させ、それによって、等 価で反対の曲げモーメントを形成させる工程を含む、対称面に対称に配置された 相対する層の複数のペアを有する多層ラミネート式構造のひずみをできるだけ抑 える方法。 22.2つの面とその間の対称面を有する中央に配置された銅層、 その対称面の反対側に等距離に配置され、それぞれが、その中央に配置された 層の面の各一方を背にしたシアネートエステル/エポキシ−延伸膨張ポリテトラ フルオロエチレン(CE/E−ePTFE)誘電体の2つの第1層、 銅層の第1ペアであって、その銅層の各々が、互いにその対称面から等距離に あって、その第1ぺアのその銅層の各々がそのシアネートエステル/エポキシ− 延伸膨張ポリテトラフルオロエチレン誘電体層の各一方を背にした銅層の第1ペ ア、 その対称面の相対する側に等距離に配置され、それぞれが、その銅層の第1ペ アの各一方をそれぞれが背にしたビスマレイミド−ト リアジン(BT)−エポキシ/ガラス誘電体の2つの第1層、 銅の導電体層のペアであって、その銅の導電体層の各々が、互いにその対称面 から等距離にあって、そのビスマレイミド−トリアジン−エポキシ/ガラス誘電 体層の各一方を背にした銅の導電体層のペア、 その対称面の相対する側に等距離に配置され、それぞれが、その銅の伝導性層 の面の各一方を背にしたシアネートエステル/エポキシ−延伸膨張ポリテトラフ ルオロエチレンの2つの第2誘電体層、及び 互いにその対称面から等距離にあるCu/Ni/Auの2つの層であって、そ の各々が、ビスマレイミド−トリアジン−エポキシ/ガラス誘電体層の各一方を 背にしたCu/Ni/Auの2つの層、 を備えたマイクロチップ用基材。 23.その対称面から互いに等距離にあるハンダマスク層のペアであって、そ のハンダマスク層の各々がその2つのCu/Ni/Au層の各一方を背にしたハ ンダマスク層のペアをさらに備えた請求項22に記載のマイクロチップ用基材。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US08/745,972 | 1996-11-08 | ||
US08/745,972 US5888631A (en) | 1996-11-08 | 1996-11-08 | Method for minimizing warp in the production of electronic assemblies |
PCT/US1997/018638 WO1998020555A1 (en) | 1996-11-08 | 1997-10-17 | Method for minimizing warp in the production of electronic assemblies |
Publications (3)
Publication Number | Publication Date |
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JP2000505245A true JP2000505245A (ja) | 2000-04-25 |
JP2000505245A5 JP2000505245A5 (ja) | 2005-06-16 |
JP5175009B2 JP5175009B2 (ja) | 2013-04-03 |
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Application Number | Title | Priority Date | Filing Date |
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JP52141498A Expired - Lifetime JP5175009B2 (ja) | 1996-11-08 | 1997-10-17 | 電子基材の製造におけるひずみ抑制方法、ラミネート式基材及びマイクロチップ用基材 |
Country Status (4)
Country | Link |
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US (2) | US5888631A (ja) |
JP (1) | JP5175009B2 (ja) |
AU (1) | AU4904497A (ja) |
WO (1) | WO1998020555A1 (ja) |
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-
1997
- 1997-10-17 AU AU49044/97A patent/AU4904497A/en not_active Abandoned
- 1997-10-17 WO PCT/US1997/018638 patent/WO1998020555A1/en active Application Filing
- 1997-10-17 JP JP52141498A patent/JP5175009B2/ja not_active Expired - Lifetime
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1998
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JP2006179925A (ja) * | 2004-12-21 | 2006-07-06 | E I Du Pont De Nemours & Co | 容量デバイス、有機誘電ラミネート、およびそのようなデバイスを組み込んだプリント配線板、ならびにそれらの製造方法 |
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Publication number | Publication date |
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US6183592B1 (en) | 2001-02-06 |
AU4904497A (en) | 1998-05-29 |
WO1998020555A1 (en) | 1998-05-14 |
US5888631A (en) | 1999-03-30 |
JP5175009B2 (ja) | 2013-04-03 |
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