JP2000503813A - バリヤのない半導体メモリ装置を製造する方法 - Google Patents

バリヤのない半導体メモリ装置を製造する方法

Info

Publication number
JP2000503813A
JP2000503813A JP10516109A JP51610998A JP2000503813A JP 2000503813 A JP2000503813 A JP 2000503813A JP 10516109 A JP10516109 A JP 10516109A JP 51610998 A JP51610998 A JP 51610998A JP 2000503813 A JP2000503813 A JP 2000503813A
Authority
JP
Japan
Prior art keywords
layer
dielectric
memory device
electrode
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10516109A
Other languages
English (en)
Japanese (ja)
Inventor
ヒンターマイアー フランク
シンドラー ギュンター
ハルトナー ヴァルター
マズレ―エスペヨ カルロス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JP2000503813A publication Critical patent/JP2000503813A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
JP10516109A 1996-09-30 1997-09-11 バリヤのない半導体メモリ装置を製造する方法 Pending JP2000503813A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19640211.5 1996-09-30
DE19640211A DE19640211A1 (de) 1996-09-30 1996-09-30 Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen
PCT/DE1997/002034 WO1998015008A1 (de) 1996-09-30 1997-09-11 Verfahren zur herstellung barrierenfreier halbleiterspeicheranordnungen

Publications (1)

Publication Number Publication Date
JP2000503813A true JP2000503813A (ja) 2000-03-28

Family

ID=7807377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10516109A Pending JP2000503813A (ja) 1996-09-30 1997-09-11 バリヤのない半導体メモリ装置を製造する方法

Country Status (7)

Country Link
EP (1) EP0931348A1 (de)
JP (1) JP2000503813A (de)
KR (1) KR20000036201A (de)
CN (1) CN1231768A (de)
DE (1) DE19640211A1 (de)
TW (1) TW388952B (de)
WO (1) WO1998015008A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19935130C1 (de) * 1999-07-27 2001-02-22 Siemens Ag Verfahren zur Herstellung eines Kontaktloches für ein Halbleiterspeicherbauelement
US6756620B2 (en) * 2001-06-29 2004-06-29 Intel Corporation Low-voltage and interface damage-free polymer memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0370407A1 (de) * 1988-11-18 1990-05-30 Nec Corporation Halbleiterspeicherbauteil vom Typ 1-transistor-1-Kondensator-Speicherzelle
US5116776A (en) * 1989-11-30 1992-05-26 Sgs-Thomson Microelectronics, Inc. Method of making a stacked copacitor for dram cell
JPH0777237B2 (ja) * 1993-01-04 1995-08-16 日本電気株式会社 半導体記憶装置及びその製造方法
US5439840A (en) * 1993-08-02 1995-08-08 Motorola, Inc. Method of forming a nonvolatile random access memory capacitor cell having a metal-oxide dielectric

Also Published As

Publication number Publication date
TW388952B (en) 2000-05-01
KR20000036201A (ko) 2000-06-26
EP0931348A1 (de) 1999-07-28
CN1231768A (zh) 1999-10-13
DE19640211A1 (de) 1998-04-02
WO1998015008A1 (de) 1998-04-09

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