JP2000348493A - 不揮発性メモリ回路 - Google Patents

不揮発性メモリ回路

Info

Publication number
JP2000348493A
JP2000348493A JP15611399A JP15611399A JP2000348493A JP 2000348493 A JP2000348493 A JP 2000348493A JP 15611399 A JP15611399 A JP 15611399A JP 15611399 A JP15611399 A JP 15611399A JP 2000348493 A JP2000348493 A JP 2000348493A
Authority
JP
Japan
Prior art keywords
reference voltage
voltage
cell
state
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15611399A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000348493A5 (Direct
Inventor
Shinji Kotani
信二 小谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15611399A priority Critical patent/JP2000348493A/ja
Priority to US09/569,301 priority patent/US6246608B1/en
Publication of JP2000348493A publication Critical patent/JP2000348493A/ja
Publication of JP2000348493A5 publication Critical patent/JP2000348493A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP15611399A 1999-06-03 1999-06-03 不揮発性メモリ回路 Pending JP2000348493A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15611399A JP2000348493A (ja) 1999-06-03 1999-06-03 不揮発性メモリ回路
US09/569,301 US6246608B1 (en) 1999-06-03 2000-05-11 Non-volatile memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15611399A JP2000348493A (ja) 1999-06-03 1999-06-03 不揮発性メモリ回路

Publications (2)

Publication Number Publication Date
JP2000348493A true JP2000348493A (ja) 2000-12-15
JP2000348493A5 JP2000348493A5 (Direct) 2005-06-16

Family

ID=15620608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15611399A Pending JP2000348493A (ja) 1999-06-03 1999-06-03 不揮発性メモリ回路

Country Status (2)

Country Link
US (1) US6246608B1 (Direct)
JP (1) JP2000348493A (Direct)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285223A (ja) * 2004-03-30 2005-10-13 Renesas Technology Corp 不揮発性半導体記憶装置及びそのデータ書き換え方法
US7269070B2 (en) 2005-08-23 2007-09-11 Samsung Electronics Co., Ltd. Flash memory device with multiple erase voltage levels
JP2009252255A (ja) * 2008-04-01 2009-10-29 Renesas Technology Corp 不揮発性半導体記憶装置
WO2011043012A1 (ja) * 2009-10-05 2011-04-14 パナソニック株式会社 不揮発性半導体記憶装置、信号処理システム、及び信号処理システムの制御方法、並びに不揮発性半導体記憶装置の書き換え方法
JP2012018744A (ja) * 2010-07-09 2012-01-26 Hynix Semiconductor Inc 半導体メモリ素子の動作方法
JP2012069199A (ja) * 2010-09-22 2012-04-05 Toshiba Corp 半導体記憶装置
JP2013515330A (ja) * 2009-12-21 2013-05-02 サンディスク スリーディー，エルエルシー マルチレベル・ライトワンス・メモリ・セルを備える書き換え可能メモリデバイス

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001273796A (ja) * 2000-03-29 2001-10-05 Nec Microsystems Ltd センスアンプ回路
JP4663094B2 (ja) * 2000-10-13 2011-03-30 株式会社半導体エネルギー研究所 半導体装置
US7087954B2 (en) * 2001-08-30 2006-08-08 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
EP1324342B1 (en) * 2001-12-28 2008-07-16 STMicroelectronics S.r.l. Programming method for a multilevel memory cell
US6829174B2 (en) * 2003-01-30 2004-12-07 Macronix International Co., Ltd. Method of narrowing threshold voltage distribution
EP1503384A3 (en) * 2003-07-21 2007-07-18 Macronix International Co., Ltd. Method of programming memory
US6778437B1 (en) * 2003-08-07 2004-08-17 Advanced Micro Devices, Inc. Memory circuit for providing word line redundancy in a memory sector
US7177200B2 (en) * 2004-02-10 2007-02-13 Msystems Ltd. Two-phase programming of a flash memory
JP2006286118A (ja) * 2005-04-01 2006-10-19 Matsushita Electric Ind Co Ltd 閾値電圧制御機能を有する不揮発性記憶装置
US7224619B2 (en) * 2005-09-09 2007-05-29 Macronix International Co., Ltd. Method and apparatus for protection from over-erasing nonvolatile memory cells
US7403427B2 (en) * 2005-11-21 2008-07-22 Elite Semiconductor Memory Technology, Inc. Method and apparatus for reducing stress in word line driver transistors during erasure
US7394714B2 (en) * 2006-09-07 2008-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Circuit implementation of a dynamic power supply for SRAM core array
US7852695B2 (en) * 2008-06-17 2010-12-14 Oracle America, Inc. Single-ended differential signal amplification and data reading

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105148B2 (ja) 1988-02-24 1995-11-13 日本電気株式会社 不揮発性半導体記憶装置
JP3392604B2 (ja) 1995-11-14 2003-03-31 株式会社東芝 不揮発性半導体記憶装置
KR100223868B1 (ko) * 1996-07-12 1999-10-15 구본준 비휘발성 메모리를 프로그램하는 방법
JP3114630B2 (ja) * 1996-10-03 2000-12-04 日本電気株式会社 不揮発性半導体メモリおよび書込み読出し方法
JPH1125681A (ja) * 1997-06-27 1999-01-29 Nec Corp 不揮発性半導体記憶装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285223A (ja) * 2004-03-30 2005-10-13 Renesas Technology Corp 不揮発性半導体記憶装置及びそのデータ書き換え方法
US7269070B2 (en) 2005-08-23 2007-09-11 Samsung Electronics Co., Ltd. Flash memory device with multiple erase voltage levels
JP2009252255A (ja) * 2008-04-01 2009-10-29 Renesas Technology Corp 不揮発性半導体記憶装置
WO2011043012A1 (ja) * 2009-10-05 2011-04-14 パナソニック株式会社 不揮発性半導体記憶装置、信号処理システム、及び信号処理システムの制御方法、並びに不揮発性半導体記憶装置の書き換え方法
JP2013515330A (ja) * 2009-12-21 2013-05-02 サンディスク スリーディー，エルエルシー マルチレベル・ライトワンス・メモリ・セルを備える書き換え可能メモリデバイス
JP2012018744A (ja) * 2010-07-09 2012-01-26 Hynix Semiconductor Inc 半導体メモリ素子の動作方法
JP2012069199A (ja) * 2010-09-22 2012-04-05 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
US6246608B1 (en) 2001-06-12

Similar Documents

Publication Publication Date Title
KR101359850B1 (ko) 메모리 소자의 데이터 라인 관리
JP4510060B2 (ja) 不揮発性半導体記憶装置の読み出し／書き込み制御方法
JP5250117B2 (ja) メモリのための適応消去及びソフトプログラミング
US7489544B2 (en) Flash memory device having multi-level cell and reading and programming method thereof
KR100376234B1 (ko) 불휘발성 반도체 기억 장치
US7738294B2 (en) Programming multilevel cell memory arrays
JP2000348493A (ja) 不揮発性メモリ回路
JP3420121B2 (ja) 不揮発性半導体記憶装置
US8570801B2 (en) Method of programming a semiconductor memory device
JP5150245B2 (ja) 半導体記憶装置
JP2022519866A (ja) フラッシュメモリデバイス
US8593876B2 (en) Sensing scheme in a memory device
US7405977B2 (en) Flash memory device with improved read speed
JP2010067327A (ja) 不揮発性半導体記憶装置
TWI569274B (zh) 堆疊式記憶體陣列裝置之感測操作
US7733705B2 (en) Reduction of punch-through disturb during programming of a memory device
US20170076806A1 (en) Access line management in a memory device
EP1061524A2 (en) Flash memory with copy and transfer function
JP2008016112A (ja) 半導体記憶装置
JP7309923B2 (ja) フラッシュメモリデバイスにおけるセンス回路および検知動作方法
JP2011134422A (ja) 不揮発性半導体記憶装置
JP3905936B2 (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040915

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040915

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060425

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060615

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060926