JP2000339229A5 - - Google Patents

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Publication number
JP2000339229A5
JP2000339229A5 JP1999152560A JP15256099A JP2000339229A5 JP 2000339229 A5 JP2000339229 A5 JP 2000339229A5 JP 1999152560 A JP1999152560 A JP 1999152560A JP 15256099 A JP15256099 A JP 15256099A JP 2000339229 A5 JP2000339229 A5 JP 2000339229A5
Authority
JP
Japan
Prior art keywords
storage means
control signal
output
data
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999152560A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000339229A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP11152560A priority Critical patent/JP2000339229A/ja
Priority claimed from JP11152560A external-priority patent/JP2000339229A/ja
Priority to US09/413,196 priority patent/US6385746B1/en
Publication of JP2000339229A publication Critical patent/JP2000339229A/ja
Publication of JP2000339229A5 publication Critical patent/JP2000339229A5/ja
Pending legal-status Critical Current

Links

JP11152560A 1999-05-31 1999-05-31 メモリテスト回路 Pending JP2000339229A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11152560A JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路
US09/413,196 US6385746B1 (en) 1999-05-31 1999-10-05 Memory test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11152560A JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路

Publications (2)

Publication Number Publication Date
JP2000339229A JP2000339229A (ja) 2000-12-08
JP2000339229A5 true JP2000339229A5 (enExample) 2005-10-27

Family

ID=15543156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11152560A Pending JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路

Country Status (2)

Country Link
US (1) US6385746B1 (enExample)
JP (1) JP2000339229A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6640321B1 (en) * 2000-04-14 2003-10-28 Lsi Logic Corporation Built-in self-repair of semiconductor memory with redundant row testing using background pattern
KR100374636B1 (ko) * 2000-10-18 2003-03-04 삼성전자주식회사 결함 테스트 및 분석 회로를 구비하는 반도체 장치 및 결함 분석 방법
EP1369878A1 (en) * 2002-06-04 2003-12-10 Infineon Technologies AG System for testing a group of functionally independent memories and for replacing failing memory words
TW591393B (en) * 2003-01-22 2004-06-11 Fujitsu Ltd Memory controller
JP4381014B2 (ja) 2003-03-18 2009-12-09 株式会社ルネサステクノロジ 半導体集積回路
WO2009096141A1 (ja) * 2008-01-29 2009-08-06 Panasonic Corporation メモリアクセスタイミング調整装置及びメモリアクセスタイミング調整方法
KR100979248B1 (ko) * 2009-02-20 2010-09-02 주식회사 네오셈 프로토콜변환보드를 사용한 ssd 소자 테스트시스템

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986004686A1 (fr) * 1985-01-31 1986-08-14 Hitachi, Ltd. Generateur de configurations de controle
US4833677A (en) * 1987-06-12 1989-05-23 The United States Of America As Represented By The Secretary Of The Air Force Easily testable high speed architecture for large RAMS
JP3343556B2 (ja) 1991-10-12 2002-11-11 株式会社日立製作所 記憶システム
JPH05189304A (ja) 1992-01-08 1993-07-30 Fujitsu Ltd 半導体記憶装置
US6021459A (en) * 1997-04-23 2000-02-01 Micron Technology, Inc. Memory system having flexible bus structure and method
US5995731A (en) * 1997-12-29 1999-11-30 Motorola, Inc. Multiple BIST controllers for testing multiple embedded memory arrays

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