JP2000339229A - メモリテスト回路 - Google Patents

メモリテスト回路

Info

Publication number
JP2000339229A
JP2000339229A JP11152560A JP15256099A JP2000339229A JP 2000339229 A JP2000339229 A JP 2000339229A JP 11152560 A JP11152560 A JP 11152560A JP 15256099 A JP15256099 A JP 15256099A JP 2000339229 A JP2000339229 A JP 2000339229A
Authority
JP
Japan
Prior art keywords
memory
data
address
test
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11152560A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000339229A5 (enExample
Inventor
Takashi Tatsumi
隆 辰巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11152560A priority Critical patent/JP2000339229A/ja
Priority to US09/413,196 priority patent/US6385746B1/en
Publication of JP2000339229A publication Critical patent/JP2000339229A/ja
Publication of JP2000339229A5 publication Critical patent/JP2000339229A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP11152560A 1999-05-31 1999-05-31 メモリテスト回路 Pending JP2000339229A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11152560A JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路
US09/413,196 US6385746B1 (en) 1999-05-31 1999-10-05 Memory test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11152560A JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路

Publications (2)

Publication Number Publication Date
JP2000339229A true JP2000339229A (ja) 2000-12-08
JP2000339229A5 JP2000339229A5 (enExample) 2005-10-27

Family

ID=15543156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11152560A Pending JP2000339229A (ja) 1999-05-31 1999-05-31 メモリテスト回路

Country Status (2)

Country Link
US (1) US6385746B1 (enExample)
JP (1) JP2000339229A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7457996B2 (en) 2003-03-18 2008-11-25 Renesas Technology Corp. Semiconductor integrated circuit capable of testing with small scale circuit configuration

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6640321B1 (en) * 2000-04-14 2003-10-28 Lsi Logic Corporation Built-in self-repair of semiconductor memory with redundant row testing using background pattern
KR100374636B1 (ko) * 2000-10-18 2003-03-04 삼성전자주식회사 결함 테스트 및 분석 회로를 구비하는 반도체 장치 및 결함 분석 방법
EP1369878A1 (en) * 2002-06-04 2003-12-10 Infineon Technologies AG System for testing a group of functionally independent memories and for replacing failing memory words
TW591393B (en) * 2003-01-22 2004-06-11 Fujitsu Ltd Memory controller
WO2009096141A1 (ja) * 2008-01-29 2009-08-06 Panasonic Corporation メモリアクセスタイミング調整装置及びメモリアクセスタイミング調整方法
KR100979248B1 (ko) * 2009-02-20 2010-09-02 주식회사 네오셈 프로토콜변환보드를 사용한 ssd 소자 테스트시스템

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986004686A1 (fr) * 1985-01-31 1986-08-14 Hitachi, Ltd. Generateur de configurations de controle
US4833677A (en) * 1987-06-12 1989-05-23 The United States Of America As Represented By The Secretary Of The Air Force Easily testable high speed architecture for large RAMS
JP3343556B2 (ja) 1991-10-12 2002-11-11 株式会社日立製作所 記憶システム
JPH05189304A (ja) 1992-01-08 1993-07-30 Fujitsu Ltd 半導体記憶装置
US6021459A (en) * 1997-04-23 2000-02-01 Micron Technology, Inc. Memory system having flexible bus structure and method
US5995731A (en) * 1997-12-29 1999-11-30 Motorola, Inc. Multiple BIST controllers for testing multiple embedded memory arrays

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7457996B2 (en) 2003-03-18 2008-11-25 Renesas Technology Corp. Semiconductor integrated circuit capable of testing with small scale circuit configuration

Also Published As

Publication number Publication date
US6385746B1 (en) 2002-05-07

Similar Documents

Publication Publication Date Title
KR0174631B1 (ko) 다중 메모리 뱅크 선택을 위한 방법 빛 장치
US6931483B2 (en) Memory device having different burst order addressing for read and write operations
US6697287B2 (en) Memory controller and memory system apparatus
JPH11134243A (ja) 記憶装置の制御装置及びデータ処理システムにおける記憶装置の制御方法
US6370627B1 (en) Memory device command buffer apparatus and method and memory devices and computer systems using same
US7778090B2 (en) Buffer circuit for a memory module
KR20080078248A (ko) 뱅크 ｉｄ를 이용할 수 있는 메모리 서브 시스템과 그 방법
JP2000339229A (ja) メモリテスト回路
KR20090007412A (ko) 저장 용량이 큰 멀티 미디어 카드
US6819598B2 (en) Memory module self identification
US7152150B2 (en) DRAM having SRAM equivalent interface
US20070028037A1 (en) Memory system with automatic dual-buffering
JP2002358232A (ja) メモリアクセス装置
US6826088B2 (en) Method and integrated circuit capable of reading and writing data simultaneously
US20250363067A1 (en) Semiconductor apparatus and semiconductor system
US7231487B2 (en) Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards
JP2000322894A (ja) 半導体記憶装置
KR100612127B1 (ko) 메모리 모듈 테스트 방법 및 이를 위한 메모리 모듈의 허브
US7395399B2 (en) Control circuit to enable high data rate access to a DRAM with a plurality of areas
JPH04106793A (ja) メモリインタフェース回路
JP4761120B2 (ja) 電子機器、画像形成装置
JPS62216059A (ja) 記憶装置チエツク方式
JPH10188594A (ja) 不良アドレスの冗長救済方法、半導体記憶装置およびそれを用いたコンピュータシステム
JP2000187620A (ja) 半導体メモリ装置
JP2006120186A (ja) 半導体集積回路およびそれを用いた画像処理システム

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050802

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050802

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20060123

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071120

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20071101

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080311