JPH10228412A5 - - Google Patents

Info

Publication number
JPH10228412A5
JPH10228412A5 JP1998000153A JP15398A JPH10228412A5 JP H10228412 A5 JPH10228412 A5 JP H10228412A5 JP 1998000153 A JP1998000153 A JP 1998000153A JP 15398 A JP15398 A JP 15398A JP H10228412 A5 JPH10228412 A5 JP H10228412A5
Authority
JP
Japan
Prior art keywords
memory
column address
data output
address strobe
strobe signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998000153A
Other languages
English (en)
Japanese (ja)
Other versions
JP3930629B2 (ja
JPH10228412A (ja
Filing date
Publication date
Priority claimed from US08/775,315 external-priority patent/US6034919A/en
Application filed filed Critical
Publication of JPH10228412A publication Critical patent/JPH10228412A/ja
Publication of JPH10228412A5 publication Critical patent/JPH10228412A5/ja
Application granted granted Critical
Publication of JP3930629B2 publication Critical patent/JP3930629B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP00015398A 1996-12-31 1998-01-05 Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置 Expired - Lifetime JP3930629B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US775315 1991-10-11
US08/775,315 US6034919A (en) 1996-12-31 1996-12-31 Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices

Publications (3)

Publication Number Publication Date
JPH10228412A JPH10228412A (ja) 1998-08-25
JPH10228412A5 true JPH10228412A5 (enExample) 2005-07-28
JP3930629B2 JP3930629B2 (ja) 2007-06-13

Family

ID=25104027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00015398A Expired - Lifetime JP3930629B2 (ja) 1996-12-31 1998-01-05 Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置

Country Status (4)

Country Link
US (1) US6034919A (enExample)
EP (1) EP0851425B1 (enExample)
JP (1) JP3930629B2 (enExample)
DE (1) DE69719943T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617356B2 (en) * 2002-12-31 2009-11-10 Intel Corporation Refresh port for a dynamic memory
TWI263899B (en) * 2004-05-07 2006-10-11 Via Tech Inc Expandable optical disk recording and playing system and main board thereof
CN102955497A (zh) * 2011-08-18 2013-03-06 鸿富锦精密工业（深圳）有限公司 安装有固态硬盘的主板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data
US5457659A (en) * 1994-07-19 1995-10-10 Micron Technology, Inc. Programmable dynamic random access memory (DRAM)
JP3160477B2 (ja) * 1994-09-30 2001-04-25 株式会社東芝 半導体メモリ及びそれに用いられるパルス信号発生回路
US5490114A (en) * 1994-12-22 1996-02-06 International Business Machines Corporation High performance extended data out
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5526320A (en) * 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5721859A (en) * 1994-12-23 1998-02-24 Micron Technology, Inc. Counter control circuit in a burst memory
JPH08297965A (ja) * 1995-04-27 1996-11-12 Mitsubishi Electric Corp 半導体集積回路装置
US5546344A (en) * 1995-06-06 1996-08-13 Cirrus Logic, Inc. Extended data output DRAM interface
US5555209A (en) * 1995-08-02 1996-09-10 Simple Technology, Inc. Circuit for latching data signals from DRAM memory
KR0167687B1 (ko) * 1995-09-11 1999-02-01 김광호 고속액세스를 위한 데이타 출력패스를 구비하는 반도체 메모리장치
US5644549A (en) * 1996-03-21 1997-07-01 Act Corporation Apparatus for accessing an extended data output dynamic random access memory

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