JP3930629B2 - Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置 - Google Patents

Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置 Download PDF

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Publication number
JP3930629B2
JP3930629B2 JP00015398A JP15398A JP3930629B2 JP 3930629 B2 JP3930629 B2 JP 3930629B2 JP 00015398 A JP00015398 A JP 00015398A JP 15398 A JP15398 A JP 15398A JP 3930629 B2 JP3930629 B2 JP 3930629B2
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JP
Japan
Prior art keywords
memory
column address
data output
extended data
address strobe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP00015398A
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English (en)
Japanese (ja)
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JPH10228412A (ja
JPH10228412A5 (enExample
Inventor
ロバート・ダブリュー・ヌーナン・ザ・セカンド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
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Compaq Computer Corp
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Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of JPH10228412A publication Critical patent/JPH10228412A/ja
Publication of JPH10228412A5 publication Critical patent/JPH10228412A5/ja
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Publication of JP3930629B2 publication Critical patent/JP3930629B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time

Landscapes

  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
JP00015398A 1996-12-31 1998-01-05 Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置 Expired - Lifetime JP3930629B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US775315 1991-10-11
US08/775,315 US6034919A (en) 1996-12-31 1996-12-31 Method and apparatus for using extended-data output memory devices in a system designed for fast page mode memory devices

Publications (3)

Publication Number Publication Date
JPH10228412A JPH10228412A (ja) 1998-08-25
JPH10228412A5 JPH10228412A5 (enExample) 2005-07-28
JP3930629B2 true JP3930629B2 (ja) 2007-06-13

Family

ID=25104027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP00015398A Expired - Lifetime JP3930629B2 (ja) 1996-12-31 1998-01-05 Ｆｐｍメモリ・デバイス用に設計されたメモリ・システムにおいてｅｄｏメモリ・デバイスを使用するための方法および装置

Country Status (4)

Country Link
US (1) US6034919A (enExample)
EP (1) EP0851425B1 (enExample)
JP (1) JP3930629B2 (enExample)
DE (1) DE69719943T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7617356B2 (en) * 2002-12-31 2009-11-10 Intel Corporation Refresh port for a dynamic memory
TWI263899B (en) * 2004-05-07 2006-10-11 Via Tech Inc Expandable optical disk recording and playing system and main board thereof
CN102955497A (zh) * 2011-08-18 2013-03-06 鸿富锦精密工业（深圳）有限公司 安装有固态硬盘的主板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data
US5457659A (en) * 1994-07-19 1995-10-10 Micron Technology, Inc. Programmable dynamic random access memory (DRAM)
JP3160477B2 (ja) * 1994-09-30 2001-04-25 株式会社東芝 半導体メモリ及びそれに用いられるパルス信号発生回路
US5490114A (en) * 1994-12-22 1996-02-06 International Business Machines Corporation High performance extended data out
US5721859A (en) * 1994-12-23 1998-02-24 Micron Technology, Inc. Counter control circuit in a burst memory
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5526320A (en) * 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
JPH08297965A (ja) * 1995-04-27 1996-11-12 Mitsubishi Electric Corp 半導体集積回路装置
US5546344A (en) * 1995-06-06 1996-08-13 Cirrus Logic, Inc. Extended data output DRAM interface
US5555209A (en) * 1995-08-02 1996-09-10 Simple Technology, Inc. Circuit for latching data signals from DRAM memory
KR0167687B1 (ko) * 1995-09-11 1999-02-01 김광호 고속액세스를 위한 데이타 출력패스를 구비하는 반도체 메모리장치
US5644549A (en) * 1996-03-21 1997-07-01 Act Corporation Apparatus for accessing an extended data output dynamic random access memory

Also Published As

Publication number Publication date
EP0851425A2 (en) 1998-07-01
DE69719943T2 (de) 2003-09-04
US6034919A (en) 2000-03-07
JPH10228412A (ja) 1998-08-25
EP0851425B1 (en) 2003-03-19
EP0851425A3 (en) 1998-12-30
DE69719943D1 (de) 2003-04-24

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