JP2000174225A - 半導体集積回路装置およびその製造方法 - Google Patents
半導体集積回路装置およびその製造方法Info
- Publication number
- JP2000174225A JP2000174225A JP10341599A JP34159998A JP2000174225A JP 2000174225 A JP2000174225 A JP 2000174225A JP 10341599 A JP10341599 A JP 10341599A JP 34159998 A JP34159998 A JP 34159998A JP 2000174225 A JP2000174225 A JP 2000174225A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- mis transistor
- semiconductor integrated
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10341599A JP2000174225A (ja) | 1998-12-01 | 1998-12-01 | 半導体集積回路装置およびその製造方法 |
| TW088119931A TW462126B (en) | 1998-12-01 | 1999-11-16 | Semiconductor integrated circuit apparatus and its manufacturing method |
| KR1019990052132A KR100712972B1 (ko) | 1998-12-01 | 1999-11-23 | 반도체 집적회로 장치 및 그 제조방법 |
| US09/452,173 US6734479B1 (en) | 1998-12-01 | 1999-12-01 | Semiconductor integrated circuit device and the method of producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10341599A JP2000174225A (ja) | 1998-12-01 | 1998-12-01 | 半導体集積回路装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000174225A true JP2000174225A (ja) | 2000-06-23 |
| JP2000174225A5 JP2000174225A5 (https=) | 2004-11-25 |
Family
ID=18347333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10341599A Pending JP2000174225A (ja) | 1998-12-01 | 1998-12-01 | 半導体集積回路装置およびその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6734479B1 (https=) |
| JP (1) | JP2000174225A (https=) |
| KR (1) | KR100712972B1 (https=) |
| TW (1) | TW462126B (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030006982A (ko) * | 2001-07-11 | 2003-01-23 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적회로장치 및 그 제조방법 |
| US6812540B2 (en) | 2001-12-17 | 2004-11-02 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US9082639B2 (en) | 2011-10-07 | 2015-07-14 | Canon Kabushiki Kaisha | Manufacturing method of semiconductor device |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232168B1 (en) * | 2000-08-25 | 2001-05-15 | Micron Technology, Inc. | Memory circuitry and method of forming memory circuitry |
| US6921692B2 (en) * | 2003-07-07 | 2005-07-26 | Micron Technology, Inc. | Methods of forming memory circuitry |
| US7838369B2 (en) * | 2005-08-29 | 2010-11-23 | National Semiconductor Corporation | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications |
| KR101116361B1 (ko) * | 2010-02-26 | 2012-03-09 | 주식회사 하이닉스반도체 | 반도체 장치 제조 방법 |
| US8785271B2 (en) * | 2011-01-31 | 2014-07-22 | GlobalFoundries, Inc. | DRAM cell based on conductive nanochannel plate |
| US11264323B2 (en) * | 2019-10-08 | 2022-03-01 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
| TWI870393B (zh) * | 2020-03-17 | 2025-01-21 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
| KR20230106849A (ko) * | 2022-01-07 | 2023-07-14 | 삼성전자주식회사 | 반도체 장치 |
| KR20230144284A (ko) | 2022-04-07 | 2023-10-16 | 삼성전자주식회사 | 반도체 장치 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02214155A (ja) | 1989-02-15 | 1990-08-27 | Hitachi Ltd | 半導体装置 |
| JPH0458556A (ja) | 1990-06-28 | 1992-02-25 | Sony Corp | 半導体装置 |
| JPH0936318A (ja) | 1995-07-18 | 1997-02-07 | Fujitsu Ltd | ダイナミックメモリ |
| JP3272979B2 (ja) * | 1997-01-08 | 2002-04-08 | 株式会社東芝 | 半導体装置 |
| JP3466851B2 (ja) * | 1997-01-20 | 2003-11-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JPH1168105A (ja) * | 1997-08-26 | 1999-03-09 | Mitsubishi Electric Corp | 半導体装置 |
-
1998
- 1998-12-01 JP JP10341599A patent/JP2000174225A/ja active Pending
-
1999
- 1999-11-16 TW TW088119931A patent/TW462126B/zh not_active IP Right Cessation
- 1999-11-23 KR KR1019990052132A patent/KR100712972B1/ko not_active Expired - Fee Related
- 1999-12-01 US US09/452,173 patent/US6734479B1/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030006982A (ko) * | 2001-07-11 | 2003-01-23 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적회로장치 및 그 제조방법 |
| JP2003031684A (ja) * | 2001-07-11 | 2003-01-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| US6900492B2 (en) | 2001-07-11 | 2005-05-31 | Hitachi, Ltd. | Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit |
| US6812540B2 (en) | 2001-12-17 | 2004-11-02 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US9082639B2 (en) | 2011-10-07 | 2015-07-14 | Canon Kabushiki Kaisha | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100712972B1 (ko) | 2007-04-30 |
| US6734479B1 (en) | 2004-05-11 |
| KR20000047699A (ko) | 2000-07-25 |
| TW462126B (en) | 2001-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100579365B1 (ko) | 메모리 어레이 및 지지 트랜지스터의 형성 방법, 및 이중일함수 지지 트랜지스터 및 매립형 dram 어레이를포함하는 반도체 장치 | |
| JP4151992B2 (ja) | 半導体集積回路装置 | |
| US7943444B2 (en) | Vertical floating body cell of a semiconductor device and method for fabricating the same | |
| US6448618B1 (en) | Semiconductor device and method for manufacturing the same | |
| US7576389B2 (en) | Semiconductor device and manufacture method thereof | |
| JP3599548B2 (ja) | 半導体集積回路装置の製造方法 | |
| US20080242024A1 (en) | Method of manufacturing semiconductor device | |
| US6242809B1 (en) | Integrated circuit memory devices including titanium nitride bit lines | |
| JPH11354749A (ja) | 半導体集積回路装置およびその製造方法 | |
| JP2000183313A (ja) | 半導体集積回路装置およびその製造方法 | |
| JP3617971B2 (ja) | 半導体記憶装置 | |
| JP2011192800A (ja) | 半導体装置及びその製造方法 | |
| JP2000174225A (ja) | 半導体集積回路装置およびその製造方法 | |
| JP4290921B2 (ja) | 半導体集積回路装置 | |
| US20050275006A1 (en) | [multi-gate dram with deep-trench capacitor and fabrication thereof] | |
| JP2000208729A (ja) | 半導体装置およびその製造方法 | |
| JP4334811B2 (ja) | 半導体装置の製造方法 | |
| JP4190791B2 (ja) | 半導体集積回路装置の製造方法 | |
| JP4077966B2 (ja) | 半導体装置の製造方法 | |
| JPH1126719A (ja) | 半導体集積回路装置の製造方法 | |
| JPH1117144A (ja) | 半導体集積回路装置およびその製造方法 | |
| JPH1126718A (ja) | 半導体集積回路装置の製造方法 | |
| JP2000138357A (ja) | 半導体集積回路装置の製造方法および半導体集積回路装置 | |
| US20050186743A1 (en) | Method for manufacturing semiconductor device | |
| JPH1126715A (ja) | 半導体集積回路装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040513 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060307 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060501 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060704 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20071017 |