JP2000174165A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JP2000174165A JP2000174165A JP10349109A JP34910998A JP2000174165A JP 2000174165 A JP2000174165 A JP 2000174165A JP 10349109 A JP10349109 A JP 10349109A JP 34910998 A JP34910998 A JP 34910998A JP 2000174165 A JP2000174165 A JP 2000174165A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor device
- semiconductor element
- manufacturing
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10349109A JP2000174165A (ja) | 1998-12-08 | 1998-12-08 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10349109A JP2000174165A (ja) | 1998-12-08 | 1998-12-08 | 半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000174165A true JP2000174165A (ja) | 2000-06-23 |
| JP2000174165A5 JP2000174165A5 (https=) | 2005-12-02 |
Family
ID=18401556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10349109A Withdrawn JP2000174165A (ja) | 1998-12-08 | 1998-12-08 | 半導体装置及びその製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000174165A (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268430B2 (en) | 2004-08-30 | 2007-09-11 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| JP2007281269A (ja) * | 2006-04-10 | 2007-10-25 | Nec Corp | 電子部品の実装構造およびその製造方法 |
| JP7624059B2 (ja) | 2021-03-18 | 2025-01-29 | 株式会社Fuji | 電子部品装着方法、および電子部品装着装置 |
-
1998
- 1998-12-08 JP JP10349109A patent/JP2000174165A/ja not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7268430B2 (en) | 2004-08-30 | 2007-09-11 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| US7776735B2 (en) | 2004-08-30 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| JP2007281269A (ja) * | 2006-04-10 | 2007-10-25 | Nec Corp | 電子部品の実装構造およびその製造方法 |
| JP7624059B2 (ja) | 2021-03-18 | 2025-01-29 | 株式会社Fuji | 電子部品装着方法、および電子部品装着装置 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20051014 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051014 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060227 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061031 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20061206 |