JP2000100171A5 - - Google Patents

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Publication number
JP2000100171A5
JP2000100171A5 JP1998270264A JP27026498A JP2000100171A5 JP 2000100171 A5 JP2000100171 A5 JP 2000100171A5 JP 1998270264 A JP1998270264 A JP 1998270264A JP 27026498 A JP27026498 A JP 27026498A JP 2000100171 A5 JP2000100171 A5 JP 2000100171A5
Authority
JP
Japan
Prior art keywords
bit line
line pair
sense amplifier
transfer
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998270264A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000100171A (ja
JP4413293B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP27026498A priority Critical patent/JP4413293B2/ja
Priority claimed from JP27026498A external-priority patent/JP4413293B2/ja
Priority to TW088107470A priority patent/TW425553B/zh
Priority to US09/307,758 priority patent/US6301173B2/en
Priority to KR1019990018838A priority patent/KR100351545B1/ko
Publication of JP2000100171A publication Critical patent/JP2000100171A/ja
Publication of JP2000100171A5 publication Critical patent/JP2000100171A5/ja
Application granted granted Critical
Publication of JP4413293B2 publication Critical patent/JP4413293B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP27026498A 1998-09-24 1998-09-24 リセット動作を高速化したメモリデバイス Expired - Fee Related JP4413293B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP27026498A JP4413293B2 (ja) 1998-09-24 1998-09-24 リセット動作を高速化したメモリデバイス
TW088107470A TW425553B (en) 1998-09-24 1999-05-07 Memory circuit with faster reset operation
US09/307,758 US6301173B2 (en) 1998-09-24 1999-05-10 Memory device with faster reset operation
KR1019990018838A KR100351545B1 (ko) 1998-09-24 1999-05-25 리셋 동작을 고속화시킨 메모리 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27026498A JP4413293B2 (ja) 1998-09-24 1998-09-24 リセット動作を高速化したメモリデバイス

Publications (3)

Publication Number Publication Date
JP2000100171A JP2000100171A (ja) 2000-04-07
JP2000100171A5 true JP2000100171A5 (enExample) 2005-01-20
JP4413293B2 JP4413293B2 (ja) 2010-02-10

Family

ID=17483837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27026498A Expired - Fee Related JP4413293B2 (ja) 1998-09-24 1998-09-24 リセット動作を高速化したメモリデバイス

Country Status (4)

Country Link
US (1) US6301173B2 (enExample)
JP (1) JP4413293B2 (enExample)
KR (1) KR100351545B1 (enExample)
TW (1) TW425553B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4748828B2 (ja) * 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6473356B1 (en) * 2001-11-01 2002-10-29 Virage Logic Corp. Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier
US7180792B2 (en) * 2002-02-28 2007-02-20 Stmicroelectronics Pvt. Ltd. Efficient latch array initialization
JP4462528B2 (ja) 2002-06-24 2010-05-12 株式会社日立製作所 半導体集積回路装置
DE10302650B4 (de) * 2003-01-23 2007-08-30 Infineon Technologies Ag RAM-Speicher und Steuerungsverfahren dafür
WO2004081945A1 (ja) * 2003-03-14 2004-09-23 Fujitsu Limited 半導体記憶装置、および半導体記憶装置の制御方法
US7245549B2 (en) 2003-03-14 2007-07-17 Fujitsu Limited Semiconductor memory device and method of controlling the semiconductor memory device
DE10339894B4 (de) * 2003-08-29 2006-04-06 Infineon Technologies Ag Leseverstärker-Zuschalt/Abschalt-Schaltungsanordnung
JP4646106B2 (ja) * 2004-05-25 2011-03-09 株式会社日立製作所 半導体集積回路装置
KR20060028989A (ko) * 2004-09-30 2006-04-04 엘지전자 주식회사 다중입출력 시스템에 적용되는 신호 처리 방법
DE102005000812A1 (de) * 2005-01-05 2006-07-20 Infineon Technologies Ag Integrierter Halbleiterspeicher mit Testschaltung für Leseverstärker
KR100736648B1 (ko) * 2005-03-08 2007-07-09 후지쯔 가부시끼가이샤 반도체 기억 장치 및 반도체 기억 장치의 제어 방법
US7212458B1 (en) * 2005-10-25 2007-05-01 Sigmatel, Inc. Memory, processing system and methods for use therewith
WO2007059772A2 (en) 2005-11-24 2007-05-31 Vip 1 Aps Direct sequential network addressing (dsna)
US7443751B2 (en) * 2006-12-22 2008-10-28 Qimonda North American Corp. Programmable sense amplifier multiplexer circuit with dynamic latching mode
JP4504397B2 (ja) 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
KR100876900B1 (ko) * 2007-12-05 2009-01-07 주식회사 하이닉스반도체 센스 앰프와 그의 구동 방법
US7813209B2 (en) * 2008-10-01 2010-10-12 Nanya Technology Corp. Method for reducing power consumption in a volatile memory and related device
KR101789467B1 (ko) 2017-04-06 2017-10-23 국방과학연구소 의사 랜덤 이진 수열 발생기의 고속 리셋 장치
US11581033B2 (en) 2021-06-09 2023-02-14 Powerchip Semiconductor Manufacturing Corporation Sub-sense amplifier layout scheme to reduce area

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3293219B2 (ja) * 1993-02-19 2002-06-17 株式会社日立製作所 ダイナミック型ｒａｍおよびそのデータ処理システム
JPH07130175A (ja) * 1993-09-10 1995-05-19 Toshiba Corp 半導体記憶装置
JP3862333B2 (ja) * 1996-12-10 2006-12-27 株式会社ルネサステクノロジ 半導体記憶装置
US5717645A (en) * 1997-02-07 1998-02-10 Alliance Semiconductor Corporation Random access memory with fast, compact sensing and selection architecture
JP3399787B2 (ja) * 1997-06-27 2003-04-21 富士通株式会社 半導体記憶装置
US5875141A (en) * 1997-08-14 1999-02-23 Micron Technology, Inc. Circuit and method for a memory device with P-channel isolation gates

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